DatasheetsPDF.com

ispPAC-POWR6AT6 Dataheets PDF



Part Number ispPAC-POWR6AT6
Manufacturers Lattice Semiconductor
Logo Lattice Semiconductor
Description In-System Programmable Power Supply Monitoring and Margining Controller
Datasheet ispPAC-POWR6AT6 DatasheetispPAC-POWR6AT6 Datasheet (PDF)

www.DataSheet4U.com ispPAC-POWR6AT6 In-System Programmable Power Supply Monitoring and Margining Controller April 2006 Preliminary Data Sheet ® Features ■ Power Supply Margin and Trim Functions • • • • Trim and margin up to six power supplies Dynamic voltage control through I2C Four hardware selectable voltage profiles Independent Digital Closed-Loop Trim function for each output Application Block Diagram Vout 3.3V Trim Vout Trim Vout ■ Analog Input Monitoring • Six analog monitor inputs • .

  ispPAC-POWR6AT6   ispPAC-POWR6AT6



Document
www.DataSheet4U.com ispPAC-POWR6AT6 In-System Programmable Power Supply Monitoring and Margining Controller April 2006 Preliminary Data Sheet ® Features ■ Power Supply Margin and Trim Functions • • • • Trim and margin up to six power supplies Dynamic voltage control through I2C Four hardware selectable voltage profiles Independent Digital Closed-Loop Trim function for each output Application Block Diagram Vout 3.3V Trim Vout Trim Vout ■ Analog Input Monitoring • Six analog monitor inputs • Differential input architecture for accurate remote ground sensing • 10-bit ADC for direct voltage measurements 1.8V Trim Vout POL#1 Trim Vout POL#2 Trim Vout ■ 2-Wire (I2C/SMBus™ Compatible) Interface • Readout of the ADC • Dynamic trimming/margining control POL#3 Trim ■ Other Features • • • • • Programmable analog circuitry Wide supply range, 2.8V to 3.96V In-system programmable through JTAG Industrial temperature range: -40°C to +85°C 32-pin QFN package, only 5mm x 5mm, leadfree option 6 Analog Trim Outputs 6 Analog Monitor Inputs ADC Other Board Circuitry 2.5V CPU I 2C Bus Description Lattice’s Power Manager II ispPAC-POWR6AT6 is a general-purpose power-supply monitoring and margining controller, incorporating in-system programmable analog functions implemented in non-volatile E2CMOS® technology. The ispPAC-POWR6AT6 device provides six independent analog input channels to monitor up to six power supply test points. Each of these input channels offers a differential input to support remote ground sensing. The ispPAC-POWR6AT6 incorporates six DACs for generating a trimming voltage to control the output voltage of a power supply. The trimming voltage can be set to four hardware selectable preset values (voltage profiles) or can be dynamically loaded in to the DAC through the I2C bus. Additionally, each power supply output voltage can be maintained typically within 0.5% tolerance across various load conditions using the Digital Closed Loop Control mode. The operating voltage profile can be selected using external hardware pins. Power Supply Margin/Trim Control I2 C Interface ispPAC-POWR6AT6 The on-chip 10-bit A/D converter can both be used to monitor the VMON voltage through the I2C bus as well as for implementing digital closed loop mode for maintaining the output voltage of all power supplies controlled by the monitoring and trimming section of the ispPACPOWR6AT6 device. The I2C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the VMON analog monitor inputs and load the DACs for the generation of the trimming voltages of the external DCDC converters. © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 6at6_01.0 Lattice Semiconductor Figure 1. ispPAC-POWR6AT6 Block Diagram CLTLOCK/SMBA ispPAC-POWR6AT6 Data Sheet CLTENb VCCD VMON1 Decoder TrimCell 1 DAC VCCA VPS0 VPS1 TRIM1 VMON1GS VMON2 VMON2GS VMON3 VMON3GS ADC VMON4 VMON4GS OSC TrimCell 4 DAC Control Logic TrimCell 3 DAC Set Point Registers TrimCell 2 DAC TRIM2 TRIM3 TRIM4 VMON5 VMON5GS VMON6 VMON6GS TrimCell 6 DAC TrimCell 5 DAC TRIM5 TRIM6 SCL I 2C Interface JTAG Interface SDA ispPAC-POWR6AT6 GND VCCJ TDO TDI TCK TMS 2 Lattice Semiconductor ispPAC-POWR6AT6 Data Sheet Pin Descriptions Number 7 8 6 Name VPS0 VPS1 CLTENb Pin Type Digital Input Digital Input Digital Input Voltage Range VCCD VCCD VCCD Description Trim Select Input 0 Trim Select Input 1 Enables closed loop trim process (asserted low) Signals that all TrimCells selected for closedloop trim have reached a trim locked condition. Can be configured to be compliant with SMBus Alert protocol.2 Voltage Monitor 1 Input Voltage Monitor 1 Ground Sense Voltage Monitor 2 Input Voltage Monitor 2 Ground Sense Voltage Monitor 3 Input Voltage Monitor 3 Ground Sense Voltage Monitor 4 Input Voltage Monitor 4 Ground Sense Voltage Monitor 5 Input Voltage Monitor 5 Ground Sense Voltage Monitor 6 Input Voltage Monitor 6 Ground Sense Ground Core VCC, Main Power Supply Analog Power Supply VCC for JTAG Logic Interface Pins Trim DAC Output 1 3 9 15 14 17 16 19 18 21 20 23 22 25 24 32 12 13 2 31 CLTLOCK/ SMBA VMON1 VMON1GS VMON2 VMON2GS VMON3 VMON3GS VMON4 VMON4GS VMON5 VMON5GS VMON6 VMON6GS GND VCCD4 VCCA4 VCCJ TRIM1 Open Drain Output Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Ground Power Power Power Analog Output 1 0V to 5.5V -0.3V to 5.75V -0.3V to 0.3V -0.3V to 5.75V -0.3V to 0.3V3 -0.3V to 5.75V -0.3V to 0.3V3 -0.3V to 5.75V -0.3V to 0.3V3 -0.3V to 5.75V -0.3V to 0.3V3 -0.3V to 5.75V -0.3V to 0.3V3 Ground 2.8V to 3.96V 2.8V to 3.96.


HVC ispPAC-POWR6AT6 L6316


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)