XRK79892

www.DataSheet4U.com xr JANAUARY 2005 PRELIMINARY XRK79892 REV. P1.0.1 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. FEATURES GENERAL DESCRIPTION The XRK79892 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 4x, phase aligned clock outputs. External PLL feedback is used to also provide zero delay buffer performance. The XRK79892 Intelligent Dynamic Clock Switch circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary clock, the device will switch to the good secondary clock and FIGURE 1. BLOCK DIAGRAM OF THE XRK79892 Fully Integrated PLL Intelligent Dynamic Clock Switch LVPECL Clock Outputs LVCMOS Control I/O 3.3V Operation 32-Lead LQFP Packagin Pin compatible with MPC9892i CLK_Selected INP1Bad INP0Bad Man_Override Alarm_Reset Sel_CLK Dynamic Switch Logic PLL_En Qb0 Qb0 Qb1 Qb1 ÷4 Qb2 Qb2 Qa0 Qa0 Qa1 Qa1 OR CLK0 CLK0 CLK1 CLK1 Ext_FB Ext_FB MR PLL 800-1600MHz ÷16 PRODUCT ORDERING INFORMATION PRODUCT NUMBER XRK...