Document
www.DataSheet4U.com
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FEBRUARY 2005
PRELIMINARY
XRK4991A
REV. P1.0.2
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
at the clock destination. This feature minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility. FEATURES
FUNCTIONAL DESCRIPTION
The XRK4991A 3.3V High-Speed Low-Voltage Programmable Skew Clock Buffer offers user selectable control over system clock functions to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can each drive terminated transmission lines with impedances as low as 50Ω while delivering minimal and specified output skews and full-swing logic levels (LVTTL). Each output can be hardwired to one of nine delay or function configurations. Delay increments of 0.7 to 1.5 ns are determined by the operating frequency with outputs able to skew up to ±6 time units from their nominal “zero” skew position. The completely integrated PLL allows external load and transmission line delay effects to be canceled. When this “zero delay” capability is combined with the selectable output skew functions, the user can create output-tooutput delays of up to ±12 time units. Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions allow distribution of a lowfrequency clock that can be multiplied by two or four FIGURE 1. BLOCK DIAGRAM OF THE XRK4991A
TEST PE FB_IN PHASE CLKIN FSEL SELD0 SELD1 Select Inputs SELC0 SELC1 SELB0 SELB1 SELA0 SELA1
FREQ DET FILTER
• Ref input is 5V tolerant • 3 pairs of programmable skew outputs • Low skew: 200ps same pair, 250ps all outputs • Selectable positive or negative edge
synchronization: Excellent for DSP applications
• Synchronous output enable • Output frequency: 3.75MHz to 85MHz • 2x, 4x, 1/2, and 1/4 outputs • 2 skew grades • 3-level inputs for skew and PLL range control • PLL bypass for DC testing • External feedback, internal loop filter • 12mA balanced drive outputs • 32-pin PLCC package • Jitter < 200 ps peak-to-peak (< 25 ps RMS) • Green packaging
VCO AND TIME UNIT GENERATOR
0E QD0 QD1
SKEW SELECT
QC0 QC1 QB0
MATRIX
QB1 QA0 QA1
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRK4991A PRELIMINARY 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
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REV. P1.0.2
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER XRK4991AIJ-5 XRK4991ACJ-5 XRK4991ACJ-7 XRK4991AIJ-7 ACCURACY 500 ps 500 ps 750 ps 750 ps OPERATING TEMPERATURE RANGE -40°C to +85°C 0°C to +70°C 0°C to +70°C -40°C to +85°C
FIGURE 2. PIN OUT OF THE XRK4991
SELC0
4 SELC1 SELD0 SELD1 PE VCCN QD1 QDO GND GND 5 6 7 8 9 10 11 12 13 14 QD1
3
2
1
32
31
SELB1 30 29 28 27 26 SELB0 OE SELA1 1F0 VCCN QA0 QA1 GND GND 25 24 23 22 21 20 QB0
CLKIN
XRK4991A
15 QC0
16 VCCN
17 FB_IN
18 VCCN
2
QB1
TEST 19
FSEL
GN.