3.3V PHASE-LOCK LOOP CLOCK DRIVER
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xr
OCTOBER 2005
XRK32510
3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS
REV. 1.0.1
GENER...
Description
www.DataSheet4U.com
xr
OCTOBER 2005
XRK32510
3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS
REV. 1.0.1
GENERAL DESCRIPTION
The XRK32510 is a high performance, low jitter, low skew clock driver. The XRK32510 uses phase-lock loop (PLL) tecnology to synthesize the CLK_IN signal into 10 output signals (QA), synchronized in both phase and frequency. XRK32510 features low skew, low jitter and 50% duty cycle making it a perfect fit in dual in line memory module (DIMM) board clocking, PC133 SDRAM designs and other server applications. The 10 outputs can be disabled using the Output Enable (OE) pin. By connecting the Feedback Output (FB_OUT) signal to the Feedback Input (FB_IN) signal, the propagation delay from CLK_IN to the 10 buffered Outputs is nearly zero. FIGURE 1. BLOCK DIAGRAM OF THE XRK32510
FEATURES
Spread Spectrum Clock Compatible Operating frequency range: 25MHz to 175MHz Low noise Low jitter internal PLL No external RC filter components required Meets or exceeds DPC133 registered DIMM
specification 1.1
Output Enable (OE) pin can be used to disable the
CLCK_OUT pins
Operating supply of 3.3V VDD Plastic 24 Pin TSSOP package
FB_OUT
QA0
QA1
QA2
QA3 CLK_IN
Ref
0
QA4
PLL
FB_IN
1
QA5
QA6 AVDD QA7
QA8
QA9 OE
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER XRK32510CG PACKAGE TYPE 24 Pin TSSOP OPERATING TEMPERATURE RANGE 0°C to +70°C
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
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