Document
www.DataSheet4U.com
MAY 2007
XR16V564/564D
2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO
REV. 1.0.1
GENERAL DESCRIPTION
The XR16V5641 (V564) is an enhanced quad Universal Asynchronous Receiver and Transmitter (UART) with 32 bytes of transmit and receive FIFOs, programmable transmit and receive FIFO trigger levels, automatic hardware and software flow control, and data rates of up to 16 Mbps at 4X sampling rate. Each UART has a set of registers that provide the user with operating status and control, receiver error indications, and modem serial interface controls. An internal loopback capability allows onboard diagnostics. The V564 is available in a 48-pin QFN, 64-pin LQFP, 68-pin PLCC and 80-pin LQFP packages. The 64-pin and 80-pin packages only offer the 16 mode interface, but the 48 and 68 pin packages offer an additional 68 mode interface which allows easy integration with Motorola processors. The XR16V564IV (64-pin) offers three state interrupt output while the XR16V564DIV provides continuous interrupt output. The XR16V564 is compatible with the industry standard ST16C554 and ST16C654/ 654D.
NOTE:
1 Covered by U.S. Patent #5,649,122.
FEATURES
• Pin-to-pin compatible with ST16C454, ST16C554,
TI’s TL16C754B and Philip’s SC16C754B
• Intel or Motorola Data Bus Interface select • Four independent UART channels
■ ■ ■ ■ ■ ■ ■ ■ ■ ■
Register Set Compatible to 16C550 Data rates of up to 16 Mbps 32 byte Transmit FIFO 32 byte Receive FIFO with error tags 4 Selectable TX and RX FIFO Trigger Levels Automatic Hardware (RTS/CTS) Flow Control Automatic Software (Xon/Xoff) Flow Control Programmable Xon/Xoff characters Wireless Infrared (IrDA 1.0) Encoder/Decoder Full modem interface
• 2.25V to 3.6V supply operation • Sleep Mode with automatic wake-up • Crystal oscillator or external clock input
APPLICATIONS
• Portable Appliances • Telecommunication Network Routers • Ethernet Network Routers • Cellular Data Devices • Factory Automation and Process Controls
FIGURE 1. XR16V564 BLOCK DIAGRAM
* 5 Volt Tolerant Inputs (Except XTAL1 input) UART Channel A 32 Byte TX FIFO TX & RX IR ENDEC 2.25V to 3.6V VCC GND
A2:A0 D7:D0 IOR# IOW # CSA# CSB# CSC# CSD# INTA INTB INTC INTD TXRDY# A-D RXRDY# A-D Reset 16/68# INTSEL CLKSEL Data Bus Interface
UART Regs BRG
TXA, RXA, DTRA#, DSRA#, RTSA#, CTSA#, CDA#, RIA#
32 Byte RX FIFO TXB, RXB, DTRB#, DSRB#, RTSB#, CTSB#, CDB#, RIB# TXC, RXC, DTRC#, DSRC#, RTSC#, CTSC#, CDC#, RIC# TXD, RXD, DTRD#, DSRD#, RTSD#, CTSD#, CDD#, RID# XTAL1 XTAL2
UART Channel B (same as Channel A)
UART Channel C (same as Channel A) UART Channel D (same as Channel A) Crystal Osc/Buffer
564 BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XR16V564/564D
2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO
REV. 1.0.1
FIGURE 2. PIN OUT ASSIGNMENT FOR 68-PIN PLCC PACKAGES IN 16 AND 68 MODE AND 64-PIN LQFP PACKAGES
INTSEL
CDA#
RIA#
CDD#
CDA#
RID#
GND
VCC
RXD
RXA
D7
D6
D5
D4
D3
D2
D1
D0
.