LP62S16512-I

LP62S16512-I Series Preliminary Document Title 512K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.2 512K X 16 BIT LOW VOLTAGE CMOS SRAM History Add Product Family and 55ns specification Issue Date March 20, 2002 Remark Preliminary PRELIMINARY (March, 2002, Version 0.2) AMIC Technology, Inc. LP62S16512-I Series Preliminary Features n Operating voltage: 2.7V to 3.6V n Access times: 55/70 ns (max.) n Current: Very low power version: Operating: 50mA (max.) Standby: 20µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 2.0V (min.) n Available in 48-ball CSP (8×10mm) packages 512K X 16 BIT LOW VOLTAGE CMOS SRAM General Description The LP62S16512-I is a low operating current 8,388,608bit static random access memory organized as 524,288 words by 16 bits and operates on low power voltage from 2.7V to 3.6V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable input is provided for POWER-DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2.0V. Product Family Product Family LP62S16512 Operating Temperature -40°C ~ +85°C VCC Range 2.7V~3.6V Power Dissipation Speed 55ns / 70ns Data Re...