LP61L256C

LP61L256C Preliminary Document Title 32K X 8 BIT HIGH SPEED CMOS SRAM Revision History Rev. No. 0.0 32K X 8 BIT HIGH SPEED CMOS SRAM History Initial issue Issue Date November 9, 2001 Remark Preliminary PRELIMINARY (November, 2001, Version 0.0) AMIC Technology, Inc. LP61L256C Preliminary Features n Single +3.3V power supply n Access times: 12/15 ns (max.) n Current: Operating: 120mA (max.) Standby: 5mA (max.) n Full static operation, no clock or refreshing required n n n n All inputs and outputs are directly TTL compatible Common I/O using three-state output Data retention voltage: 2V (min.) Available in 28-pin SOJ package 32K X 8 BIT HIGH SPEED CMOS SRAM General Description The LP61L256C is a high-speed, low-power 262,144-bit static random access memory organized as 32,768 words by 8 bits and operates on a single 3.3V power supply. It is built using high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Minimum standby power is drawn by this device when CE is at a high level, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 2V. Pin Configurations n SOJ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 28 27 26 25 24 23 22 21 20 19 18 17 16 15 LP61L256C PRELIMINARY (November, 2001, Version 0.0) 1 AMIC Technology, Inc. LP61L...