128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
LP61L1024
128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
Document Title 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM R...
Description
LP61L1024
128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
Document Title 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM Revision History
Rev. No.
2.0 2.1
History
Add product family and 32-pin TSSOP package Add 36 ball BGA package type
Issue Date
May 9, 2002 August 22, 2002
Remark
Final
(August, 2002, Version 2.1)
AMIC Technology, Inc.
LP61L1024
128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
Features
n Single +3.3V power supply n Access times: 12/15 ns (max.) n Current: Operating: 170mA (max.) Standby: 10mA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL compatible n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2.0V (min.) n Available in 32-pin SOJ 300 mil, 32-pin TSOP and 32pin TSSOP and 36-pin CSP packages
General Description
The LP61L1024 is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2.0V.
Product Family Product Family
Operating Temperature VCC Range
Power Dissipation Speed
Data Retention (ICCDR, Typ.) Standby (ISB1, Typ...
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