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CY28441
Clock Generator for Intel Alviso Chipset
Features
• Compliant to Intel CK410M • Supports Intel Pentium®-M CPU • Selectable CPU frequencies • Differential CPU clock pairs • 100-MHz differential SRC clocks • 96-MHz differential dot clock • 48-MHz USB clocks • SRC clocks independently stoppable through CLKREQ#[A:B] • 33-MHz PCI clock • Low-voltage frequency select input • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.3V power supply • 56-pin TSSOP package CPU x2 / x3 SRC x6 / x7 PCI x6 REF x1 DOT96 x1 USB_48 x1
Block Diagram
XIN XOUT CPU_STP# PCI_STP# CLKREQ[A:B]# FS_[C:A] VTT_PWRGD# IREF
Pin Configuration
VDD_PCI VSS_PCI PCI3 VDD_CPU PCI4 CPUT[0:1], CPUC[0:1], CPU(T/C)2_ITP] PCI5 VDD_SRC VSS_PCI SRCT[0:5], SRCC[0:5] VDD_PCI PCIF0/ITP_EN PCIF1 VTT_PWRGD#/PD VDD_PCI VDD_48 PCI[2:5] USB_48/FS_A VDD_PCIF VSS_48 PCIF[0:1] DOT96T DOT96C VDD_48 MHz FS_B/TEST_MODE DOT96T SRCT0 DOT96C SRCC0 USB_48 SRCT1 SRCC1 VDD_SRC SRCT2 SRCC2 SRCT3 SRCC3 SRC4_SATAT SRC4_SATAC VDD_SRC
VDD_REF REF
XTAL OSC PLL1
PLL Ref Freq
Divider Network
PD
PLL2
SDATA SCLK
I2C Logic
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
PCI2 PCI_STP# CPU_STP# FS_C/TEST_SEL REF VSS_REF XIN XOUT VDD_REF SDATA SCLK VSS_CPU CPUT0 CPUC0 VDD_CPU CPUT1 CPUC1 IREF VSSA VDDA CPUT2_ITP/SRCT7 CPUC2_ITP/SRCC7 VDD_SRC CLKREQA# CLKREQB# SRCT5 SRCC5 VSS_SRC
56 TSSOP
Cypress Semiconductor Corporation Document #: 38-07679 Rev. **
•
3901 North First Street
•
San Jose, CA 95134 • 408-943-2600 Revised July 13, 2004
CY28441
CY28441
Pin Description
Pin No. 33, 32 Name CLKREQA#, CLKREQB#, CPU_STP# CPUT2_ITP/SRCT7, CPUC2_ITP/SRCC7 DOT96T, DOT96C FS_A/USB_48 FS_B/TEST_MODE Type I, PU Description 3.3V LVTTL input for enabling assigned SRC clock, active LOW. CLKREQA# defaults to enable/disable SRCT/C4, CLKREQB# defaults to enable/disable SRCT/C5. Assignment can be changed via SMBUS register Byte 8. 3.3V LVTTL input for CPU_STP# active LOW.
54 36, 35
I, PU
44, 43, 41, 40 CPUT/C
O, DIF Differential CPU clock outputs. O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7 ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2 O, DIF Fixed 96-MHz clock output. I/O, SE 3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output. Refer to DC Electrical Specifications table for VIL_FS,VIH_FS specifications. I 3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Hi-Z when in test mode 0 = Hi-Z, 1 = Ref/N Refer to DC Electrical Specifications table for VIL_FS,VIH_FS specifications. 3.3V-tolerant input for CPU frequency selection. Selects test mode if pulled to greater than 2.0V when VTT_PWRGD# is asserted low. Refer to DC Electrical Specifications table for VIL_FS,VIH_FS specifications. A precision resistor is attached to this pin, which is connected to the internal current reference. 3.3V LVTTL input for PCI_STP# active LOW.
14, 15 12 16
53
FS_C/TEST_SEL
I
39 56, 3, 4, 5 55 8 9 52 46 47 26, 27
IREF PCI PCI_STP# PCIF0/ITP_EN PCIF1 REF SCLK SDATA SRC4_SATAT, SRC4_SATAC
I
O, SE 33-MHz clocks. I, PU I/O, SE 33-MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion). 1 = CPU2_ITP, 0 = SRC7 O, SE 33-MHz clock. O, SE Reference clock. 3.3V 14.318-MHz clock output. I I/O SMBus-compatible SCLOCK. SMBus-compatible SDATA.
O, DIF Differential serial reference clock. Recommended output for SATA. O, DIF Differential serial reference clocks.
24, 25, 22, SRCT/C 23, 19, 20, 17, 18, 31, 30 11 42 1,7 48 21, 28, 34 37 13 45 2,6 51 29 38 10 VDD_48 VDD_CPU VDD_PCI VDD_REF VDD_SRC VDDA VSS_48 VSS_CPU VSS_PCI VSS_REF VSS_SRC VSSA VTT_PWRGD#/PD
PWR PWR PWR PWR PWR PWR GND GND GND GND GND GND I
3.3V power supply for outputs. 3.3V power supply for outputs. 3.3V power supply for outputs. 3.3V power supply for outputs. 3.3V power supply for outputs. 3.3V power supply for PLL. Ground for outputs. Ground for outputs. Ground for outputs. Ground for outputs. Ground for outputs. Ground for PLL. 3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A, FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for asserting power-down (active HIGH). Page 2 of 20
Document #: 38-07679 Rev. **
CY28441
Pin Description
Pin No. 50 49 XIN XOUT Name Type I 14.318-MHz crystal input. O, SE 14.318-MHz crystal output. initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Description
Frequency Select Pins (FS_A, FS_B and FS_C)
Host clock frequency selection is achieved by applying the appropriate logic level.