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CY28416 Dataheets PDF



Part Number CY28416
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description Next Generation FTG
Datasheet CY28416 DatasheetCY28416 Datasheet (PDF)

www.DataSheet4U.com PRELIMINARY CY28416 Next Generation FTG for Intel® Architecture Features • Supports Intel Pentium®4-Type CPUs • Selectable CPU Frequencies • Two Differential CPU Clock Pairs • Four 100-MHz Differential SRC Clock Pairs • One CPU/SRC Selectable Differential Clock Pair • One 96-MHz Differential Dot Clock Support • Two 48-MHz Clocks • Four 33-MHz PCI Clocks • Two 33-MHz PCI Free Running Clocks • Low Voltage Frequency Select Input • I2C Support Byte/Word/Block Read/Write Capabi.

  CY28416   CY28416


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www.DataSheet4U.com PRELIMINARY CY28416 Next Generation FTG for Intel® Architecture Features • Supports Intel Pentium®4-Type CPUs • Selectable CPU Frequencies • Two Differential CPU Clock Pairs • Four 100-MHz Differential SRC Clock Pairs • One CPU/SRC Selectable Differential Clock Pair • One 96-MHz Differential Dot Clock Support • Two 48-MHz Clocks • Four 33-MHz PCI Clocks • Two 33-MHz PCI Free Running Clocks • Low Voltage Frequency Select Input • I2C Support Byte/Word/Block Read/Write Capabilities • Ideal Lexmark Spread Spectrum Profile for Maximum EMI Reduction • 3.3V Power Supply • 48-pin SSOP Package CPU x2 / x3 SRC x4 / x5 PCI x6 DOT x1 USB x2 REF x2 Block Diagram XIN XOUT Pin Configuration VDD_REF REF VDD_CPU CPUT[0:1], CPUC[0:1], CPU2/SRC4 VDD_SRC SRCT[0:3], SRCC[0:3] XTAL OSC PLL1 PLL Ref Freq Divider Network FS_[C:A] VTT_PWRGD# IREF VDD_PCI PCI[0:3] VDD_PCIF PCIF[0:1] PD VDD_48MHz PLL2 DOT96T DOT96C 48MHz0 48MHz1 SDATA SCLK I2C Logic SCLK SDATA XOUT XIN VSS_REF REF1/FS_A REF0/FS_C VDD_REF PCI0 PCI1 VDD_PCI VSS_PCI PCI2 PCI3 VSS_PCI VDD_PCI PCIF0/TESTSEL PCIF1/ITPEN VDD_48 48MHz0/FS_B 48MHz1 VSS_48 DOT96T DOT96C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VSS_CPU CPUT0 CPUC0 VDD_CPU CPUT1 CPUC1 IREF VSSA VDDA CPUT2_ITP/SRCT4 CPUC2_ITP/SRCC4 VDD_SRC VSS_SRC SRCT3 SRCC3 VDD_SRC SRCC2_SATA SRCT2_SATA SRCC1 SRCT1 VSS_SRC SRCC0 SRCT0 VTT_PWRGD#/PD 48-PIN SSOP Cypress Semiconductor Corporation Document #: 38-07657 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised February 2, 2005 CY28416 PRELIMINARY Pin Definition Pin No. 47,46,44,43 39,38 Name CPUT/C[0:1] CPUT2_ITP/SRCT4 CPUC2_ITP/SRCC4 DOT96T, DOT96C FS_A/REF1 FS_B/48 MHz0 FS_C/REF0 IREF ITP_EN/PCIF1 PCI 48 MHz1 SCLK SDATA SRCT/C[0:3] Type O, DIF Differential CPU clock output. Description CY28416 O, DIF Selectable Differential CPU or SRC clock output. ITP_EN = 0 @VTT_PWRGD# assertion PIN 39,38 = SRCT4,SRCC4 ITP_EN = 1 @VTT_PWRGD# assertion PIN 39,38 = CPUT2_ITP,CPUC2_ITP O, DIF Differential 96-MHz clock output I/O, SE 3.3V tolerant input for CPU frequency/REF clock Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. I/O, SE 3.3V tolerant input for CPU frequency/48 MHz clock Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. I/O, SE 3.3V tolerant input for CPU frequency/REF clock Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. I A precision resistor is attached to this pin, which is connected to the internal current reference. 23,24 6 20 7 42 18 9,10,13,14 21 1 2 26,27,29,30, 34,35 I/O, SE Enable SRC4 or CPU2_ITP/PCIF clock. (sampled on the VTT_PWRGD# assertion). 0 = SRC4, 1 = CPU2_ITP O, SE 33-MHz clock output. O, SE 48-MHz clock output.(Uses same control SMBus register as 48 MHz0 to control enable/disable.) I I/O SMBus compatible SCLOCK. SMBus compatible SDATA. O, DIF Differential Serial reference clock. 31,32 17 19 45 11, 16 8 33, 37 40 22 48 12, 15 5 28, 36 41 25 SRCT2_SATA, SRCC2_SATA TEST_SEL/PCIF0 VDD_48 VDD_CPU VDD_PCI VDD_REF VDD_SRC VDDA VSS_48 VSS_CPU VSS_PCI VSS_REF VSS_SRC VSSA VTT_PWRGD#/PD O, DIF Differential Serial reference clock. Recommended output for SATA I/O, SE, LVTTL input for selecting HI-Z or Normal operation/33 MHz Clock PD 0 = Normal operation, 1 = HI-Z when VTT_PWRGD# is sampled PWR PWR PWR PWR PWR PWR GND GND GND GND GND GND I, PD 3.3V power supply for outputs 3.3V power supply for outputs 3.3V power supply for outputs 3.3V power supply for outputs 3.3V power supply for outputs 3.3V power supply for PLL Ground for outputs Ground for outputs Ground for outputs Ground for outputs Ground for outputs Ground for PLL 3.3V LVTTL Input. This pin is a level-sensitive strobe used to latch the FS_A, FS_B, FS_C/TEST_SEL, and PCIF0/ITP_EN Inputs. After asserting VTT_PWRGD# (active LOW), this pin becomes a realtime input for asserting power-down (active HIGH) 14.318-MHz Crystal Input 14.318-MHz Crystal Output 4 3 XIN XOUT I O Document #: 38-07657 Rev. *A Page 2 of 15 PRELIMINARY Frequency Select Pins (FS_A, FS_B, and FS_C) Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled LOW by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A, FS_B, and FS_C input values. For all logic levels of FS_A, FS_B, and FS_C VTT_PWRGD# employs a one-shot functionality in that once a valid LOW on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FS_A, FS_B, and FS_C transitions will be ignored, except in test mode. CY28416 izes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The i.


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