VIRTEX-4

0 Virtex-4 Tri-Mode Embedded Ethernet MAC Wrapper v4.4 DS307 February 15, 2007 0 0 Product Specification Introduction The LogiCORE™ Virtex-4™ Embedded Tri-Mode Ethernet Media Access Controller (MAC) Wrapper automates the generation of HDL wrapper files for the Tri-Mode Ethernet MAC in Virtex-4 FX devices using the Xilinx CORE Generator™. VHDL and Verilog instantiation templates are available in the Libraries Guide for the Virtex-4 Ethernet MAC primitive; however, due to the complexity and the large number of ports, the CORE Generator simplifies integration of the Ethernet MAC by providing HDL examples based on user-selectable configurations. Supported Family Performance LogiCORE Facts Virtex-4 FX 10 Mbps, 100 Mbps, 1 Gbps Example Design Resources Slices LUTs FFs Block RAMs DCM BUFG Wrapper Highlights Optimized Clocking Logic Hardware Verified HDL Example Design Demonstration Test Bench Provided with Wrapper Documentation Product Specification Getting Started Guide User Guide2 HDL Example Design, Demonstration Test Bench, Scripts User Constraints File (UCF) Example FIFO connected to client I/F Demonstration Test Environment Design Tool Requirements Supported HDL Synthesis Xilinx Tools Simulation Tools (SWIFT-compliant simulator required) VHDL and/or Verilog XST 9.1i ISE™ 9.1i Mentor ModelSim® 6.1e Cadence™ IUS3 366-11121 420-12331 432-13551 4-81 0-21 2-81 Features Allows selection of one or both Ethernet MACs (EMAC0/EMAC1) from the Embedded Ethernet MAC primitive www.Da...