IS42S81600B

IS42S81600B IS42S16800B 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM ISSI MAY 2006 ® FEATURES Clock frequency: 167, 143, 133 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for hiding row access/precharge Power supply IS42S81600B IS42S16800B LVTTL interface Programmable burst length – (1, 2, 4, 8, full page) www.DataSheet4U.com OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized as follows. VDDQ VDD 3.3V 3.3V 3.3V 3.3V IS42S81600B 4M x8x4 Banks 54-pin TSOPII IS42S16800B 2M x16x4 Banks 54-pin TSOPII Programmable burst sequence: Sequential/Interleave Auto Refresh (CBR) Self Refresh with programmable refresh periods 4096 refresh cycles every 64 ms Random column address every clock cycle Programmable CAS latency (2, 3 clocks) Burst read/write and burst read/single write operations capability Burst termination by burst stop and precharge command Industrial Temperature Availability Lead-free Availability KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -6 6 – 167 – 5.4 – -7 7 10 143 100 5.4 6 -75E – 7.5 – 133 – 6 Unit ns ns Mhz Mhz ns ns Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves t...