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MT8931C Dataheets PDF



Part Number MT8931C
Manufacturers Mitel Networks
Logo Mitel Networks
Description Subscriber Network Interface Circuit
Datasheet MT8931C DatasheetMT8931C Datasheet (PDF)

® CMOS ST-BUS™ FAMILY MT8931C Subscriber Network Interface Circuit Preliminary Information Features • • • • • • • • • • • • • • www.DataSheet4U.com ISSUE 1 May 1995 ETS 300-012, CCITT I.430 and ANSI T1.605 S/T interface Full-duplex 2B+D, 192 kbit/s transmission Link activation/deactivation D-channel access contention resolution Point-to-point, point-to-multipoint and star configurations Master (NT)/Slave (TE) modes of operation Exceeds loop length requirements Complete loopback testing capa.

  MT8931C   MT8931C



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® CMOS ST-BUS™ FAMILY MT8931C Subscriber Network Interface Circuit Preliminary Information Features • • • • • • • • • • • • • • www.DataSheet4U.com ISSUE 1 May 1995 ETS 300-012, CCITT I.430 and ANSI T1.605 S/T interface Full-duplex 2B+D, 192 kbit/s transmission Link activation/deactivation D-channel access contention resolution Point-to-point, point-to-multipoint and star configurations Master (NT)/Slave (TE) modes of operation Exceeds loop length requirements Complete loopback testing capabilities On chip HDLC D-channel protocoller 8 bit Motorola/Intel microprocessor interface Microprocessor-controlled operation Mitel ST-BUS interface Low power CMOS technology Single 5 volt power supply Ordering Information MT8931CC 28 Pin Ceramic DIP MT8931CE 28 Pin Plastic DIP MT8931CP 44 Pin PLCC -40°C to +85°C Description The MT8931C Subscriber Network Interface Circuit (SNIC) implements the ETSI ETS 300-012, CCITT I.430 and ANSI T1.605 Recommendations for the ISDN S and T reference points. Providing point-topoint and point-to-multipoint digital transmission, the SNIC may be used at either end of the subscriber line (NT or TE). An HDLC D-channel protocoller is included and controlled through a Motorola/Intel microprocessor port. The MT8931C is fabricated in process. Mitel’s CMOS Applications • • • • • ISDN NT1 ISDN S or T interface ISDN Terminal Adaptor (TA) Digital sets (TE1) - 4 wire ISDN interface Digital PABXs, Digital Line Cards (NT2) DSTi DSTo ST-BUS Interface D-channel Priority Mechanism LTx S-Bus Link Interface VBias LRx F0od C4b F0b STAR/Rsto XTAL1/NT XTAL2/NC Microprocessor Interface VSS Timing and Control PLL HDLC Transceiver Link Activation Controller VDD Rsti HALF AD0-7 R/W/WR DS/RD AS/ALE CS IRQ/NDA Figure 1 - Functional Block Diagram 9-73 MT8931C Preliminary Information HALF C4b F0b F0od DSTi DSTo XTAL2/NC XTAL1/NT R/W/WR DS/RD AS/ALE CS IRQ/NDA VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD VBias LTx LRx STAR/Rsto Rsti AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 F0od DSTi DSTo NC NC NC XTAL2/NC XTAL1/NT NC R/W/WR DS/RD 6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28 NC AS/ALE CS IRQ/NDA VSS NC AD0 AD1 AD2 NC NC 44 PIN PLCC NC NC F0b C4b HALF NC VDD VBias LTx NC LRx NC STAR/Rsto Rsti NC AD7 AD6 NC AD5 AD4 AD3 NC 28 PIN PDIP/CERDIP Figure 2 - Pin Connections Pin Description Pin # DIP PLCC www.DataSheet4U.com Name HALF Description HALF Input/Output: this is an input in NT mode and an output in TE mode identifying which half of the S-interface frame is currently being written/read over the ST-BUS (HALF = 0 sampled on the falling edge of C4b within the frame pulse low window, identifies the information to be transmitted/received in the first half of the S-Bus frame while HALF=1 identifies the information to be transmitted/received into the second half of the S-Bus frame). Tying this pin to VSS or VDD in NT mode will allow the device to free run. This signal can also be accessed from the ST-BUS C-channel. 4.096 MHz Clock: a 4.096 MHz ST-BUS Data Clock input in NT mode. In TE mode an output 4.096 MHz clock phase-locked to the line data signal. Frame Pulse: an active low frame pulse input indicating the beginning of active STBUS channel times in NT mode. Frame pulse output in TE mode. Delayed Frame Pulse Output: an active low delayed frame pulse output indicating the end of active ST-BUS channels for this device. Can be used to daisy chain to other ST-BUS devices to share an ST-BUS stream. Data ST-BUS Input: a 2048 kbit/s serial PCM/data ST-BUS input with D, C, B1, and B2 channels assigned to the first four timeslots. These channels contain data to be transmitted on the line and chip control information. Data ST-BUS Output: a 2048 kbit/s serial PCM/data ST-BUS output with D, C, B1 and B2 channels assigned to the first four timeslots, respectively. The remaining timeslots are placed into high impedance. These channels contain data received from the line and chip status information. 1 2 2 3 4 3 4 7 C4b F0b F0od 5 8 DSTi 6 9 DSTo 7 13 XTAL2/IC Crystal 2/Internal Connection: in TE mode, XTAL1 and XTAL2 are to be connected to an external 4.096 MHz parallel resonant crystal for the on-chip oscillator. If XTAL1 is connected directly to a 4.096 MHz clock, this pin must be left unconnected. In NT mode, this pin must be left unconnected. XTAL1/NT Crystal 1/Network Termination Mode Select Input: for TE mode mode selection, a 4.096 MHz crystal is to be connected between the XTAL1 and XTAL2 pins, or a 4.096 MHz clock can be connected directly to XTAL1. For NT mode selection, this pin must be tied to VDD. A pull-up resistor is needed when driven by a TTL device. 8 14 9-74 Preliminary Information Pin Description (continued) Pin # DIP PLCC 9 10 16 17 Name R/W /WR DS/RD Description MT8931C Read/Write or Write Input: defines the data bus transfer as a read (R/W=1) or a write .


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