Document
Features
• Serial Peripheral Interface (SPI) Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1)
– Datasheet describes Mode 0 Operation
• 50 MHz Clock Rate • Byte Mode and Page Mode Program (1 to 256 Bytes) Operations • Sector/Block/Page Architecture
– 256 byte Pages per Sector – Eight 4 Kbyte Sectors per Block – Four uniform 32 Kbyte Blocks Self-timed Sector, Block and Chip Erase Product Identification Mode with JEDEC Standard Low-voltage Operation – 2.7V (VCC = 2.7V to 3.6V) Hardware and Software Write Protection – Device protection with Write Protect (WP) Pin – Write Enable and Write Disable Instructions – Software Write Protection: Upper 1/32, 1/16, 1/8, 1/4, 1/2 or Entire Array Flexible Op Codes for Maximum Compatibility Self-timed Program Cycle – 30 µs/Byte Typical Single Cycle Reprogramming (Erase and Program) for Status Register High Reliability – Endurance: 10,000 Write Cycles Typical 8-lead JEDEC 150mil SOIC and 8-lead Ultra Thin Small Array Package (SAP)
• • • •
High Speed Small Sectored SPI Flash Memory
1M (131,072 x 8)
• • • • •
AT25FS010
Description
www.DataSheet4U.com
The AT25FS010 provides 1,048,576 bits of serial reprogrammable Flash memory organized as 131,072 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25FS010 is available in a space-saving 8-lead JEDEC SOIC and 8-lead Ultra Thin SAP packages. Table 1. Pin Configuration
Pin Name CS SCK SI SO GND VCC WP HOLD Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Write Protect Suspends Serial Input
VCC _____
CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI
Advance Information
8-lead JEDEC SOIC
8-lead SAP
___
8 1 CS 2 ___ SO 3 WP 4 GND HOLD 7 SCK 6 SI 5
Bottom View
5167B–SFLSH–1/07
The AT25FS010 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are completely self-timed. BLOCK WRITE protection for upper 1/32, 1/16, 1/8, 1/4, 1/2 or the entire memory array is enabled by programming the status register. Separate write enable and write disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.
Absolute Maximum Ratings*
Operating Temperature....................................–40°C to +85°C Storage Temperature .....................................–65°C to +150°C Voltage on Any Pin with Respect to Ground .................................... –1.0V to +5.0V Maximum Operating Voltage ............................................ 4.2V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under “Absolute.