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PI74SSTVF16857A Dataheets PDF



Part Number PI74SSTVF16857A
Manufacturers Pericom Semiconductor
Logo Pericom Semiconductor
Description 14-Bit Registered Buffer
Datasheet PI74SSTVF16857A DatasheetPI74SSTVF16857A Datasheet (PDF)

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  PI74SSTVF16857A   PI74SSTVF16857A


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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74SSTVF16857A 14-Bit Registered Buffer Product Features • Designed for low-voltage operation, 2.5V for PC1600 ~ PC2700; 2.6V for PC3200 • Supports SSTL_2 Class I output specifications • SSTL_2 Input and Output Levels • Designed for DDR Memory • Flow-Through Architecture • Packaging Options (Lead-free packages are available): – 48-pin 240 mil wide plastic TSSOP (A) – 48-pin 173 mil wide plastic TVSOP (K) Product Description Pericom Semiconductor’s PI74SSTVF16857A series of logic circuits are produced using the Company’s advanced sub-micron CMOS technology, achieving industry leading speed. The 14-bit PI74SSTVF16857A universal bus driver is designed for 2.5V to 2.6V VDD operation and SSTL_2 I/O Levels except for the RESET input which is LVCMOS. Data flow from D to Q is controlled by the differential clock , CLK, CLK and RESET. Data is triggered on the positive edge of CLK. CLK must be used to maintain noise margins. RESET must be supported with LVCMOS levels as VREF may not be stable during power-up. RESET is asynchronous and is intended for power-up only and when low assures that all of the registers reset to the Low State, Q outputs are low, and all input receivers, data and clock, are switched off. R CLK V Logic Block Diagram CLK CLK RESET D1 VREF 38 39 34 48 35 1 Q1 D Pericom’s PI74SSTVF16857A is characterized for operation from 0° to 70°C. Product Pin Configuration TO 13 OTHER CHANNELS www.DataSheet4U.com Product Pin Description Pin Name RESET CLK CLK D Q GND VDD VDDQ VREF Description Reset (Active Low) Clock Input Clock Input Data Input Data Output Ground Core Supply Voltage Output Supply Voltage Input Reference Voltage (1) Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ Q6 Q7 VDDQ GND Q8 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 D1 D2 GND VDD D3 D4 D5 D6 D7 CLK CLK VDD GND VREF RESET D8 D9 D10 D11 D12 VDD GND D13 D14 48-Pin 39 A, K 38 11 37 36 35 34 33 32 31 30 29 28 27 26 25 Truth Table RESET L H Η H Inputs CLK X ↑ ↑ L or H CLK X ↓ ↓ L or H D X H L X Outputs Q L H L Q o( 2 ) Q9 VDDQ GND Q10 Q11 Q12 VDDQ GND Q13 Q14 Notes: 2. Output level before the 1. H = High Signal Level indicated steady state L = Low Signal Level input conditions were ↑ = Transition LOW-to-HIGH established. ↓ = Transition HIGH-to-LOW X = Irrelevant 1 PS8687 05/27/03 PI74SSTVF16857A 14-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Parame te r Storage Temperature Supply Voltage Input Voltage(1) Output Voltage(1,2) Input Clamp Current Output Clamp Current Continuous Output Current VDD, VDDQ, or GND current/pin Package Thermal Impedance A- Package K- Package Symbol Tstg VDD or VDDQ VI VO II K, VI < 0 IO K, VO < 0 IO, VO = 0 to VDDQ IDD, IDDQ or GND Ø JA Ratings –65 to 150 – 0.5 to 3.6 – 0.5 to VDD + 0.5 – 0.5 to VDDQ + 0.5 – 50 ± 50 ± 50 ±100 70 58 Units oC V mA o C/W Notes: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This current will flow only when the output is in the high state level VO > VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 PS8687 05/27/03 PI74SSTVF16857A 14-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Recommended Operating Conditions Parame te rs De s cription PC1600 P C 2700 P C 3200 Reference Voltage VREF = 0.5X VDDQ AC input High Voltage AC input Low Voltage Input Voltage DC Input High Voltage DC Input Low Voltage Input High Voltage Input Low Voltage Common- Mode Input Voltage Range Peak- to- Peak Input Voltage High- Level Output Current Low- Level Output Current Operating Free- Air Temperature 0 RESET 1.7 0.7 0.97 0.36 1.53 VDDQ +0.6 –16 16 70 mA ºC Data Inputs PC1600 P C 2700 P C 3200 D.


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