HYB39S256400CTL

HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM 256 MBit Synchronous DRAM High Performance: -7.5 fCK tCK3 tAC3 tCK2 tAC2 133 7.5 5.4 10 6 -8 125 8 6 10 6 Units MHz ns ns ns ns Multiple Burst Read with Single Write Operation Automatic Command and Controlled Precharge Data Mask for Read / Write control (x4, x8) Data Mask for byte control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 8192 refresh cycles / 64 ms (7,8 µs) Random Column Address every CLK ( 1-N Rule) Single 3.3V +/- 0.3V Power Supply LVTTL Interface versions Plastic Packages: P-TSOPII-54 400mil width (x4, x8, x16) -7.5 parts for PC133 3-3-3 operation -8 parts for PC100 2-2-2 operation Fully Synchronous to Positive Clock Edge 0 to 70 °C operating temperature Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2 & 3 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8 Full page burst length for sequential wrap around www.DataSheet4U.com The HYB39S256400/800/160CT(L) are four bank Synchronous DRAM’s organized as 4 banks x 16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with INFINEON’s advanced 0.17 µm 256MBit DRAM process technology. The device is de...