CY28347

CY28347 Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems Features Supports VIA P4M266/KM266 chipsets Supports Pentium® 4, Athlon processors Supports two DDR DIMMS Provides — Two different programmable CPU clock pairs — Six differential DDR SDRAM pairs — Two low-skew/low-jitter AGP clocks — Six low-skew/low-jitter PCI clocks — One 48M output for USB — One programmable 24M or 48M for SIO Dial-a-Frequency and Dial-a-dB features Spread Spectrum for best electromagnetic interference (EMI) reduction SMBus-compatible for programmability 56-pin SSOP and TSSOP packages Table 1. Frequency Selection Table FS(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CPU 66.80 100.20 120.00 133.33 72.00 105.00 160.00 140.00 77.00 110.00 180.00 150.00 90.00 100.00 200.00 133.33 AGP 66.80 66.80 60.00 66.67 72.00 70.00 64.00 70.00 77.00 73.33 60.00 60.00 60.00 66.67 66.67 66.67 PCI 33.40 33.40 30.00 33.33 36.00 35.00 32.00 35.00 38.50 36.67 30.00 30.00 30.00 33.33 33.33 33.33 www.DataSheet4U.com Block Diagram XIN XOUT VDDR XTAL REF0 VDDI SELP4_K7# VDDC CPUT/CPU0D_T CPUC/CPU0D_C VDDPCI FS3 FS1 PCI(3:5) PCI_F MULTSEL PCI2 PCI1 VDDAGP AGP(0:1) REF(0:1) CPUCS_T CPUCS_C Pin Configuration[1] *FS0/REF0 VSSR XIN XOUT VDDAGP *MODE/AGP0 *SELP4_K7#/AGP1 *PCI_STP# VSSAGP **FS1/PCI_F PCI1 *MULTSEL/PCI2 VSSPCI PCI3 PCI4 VDDPCI PCI5 *CPU_STP# VSS48M **FS3/48M **FS2/24_48M VDD48M VDD VSS IREF *PD# SCLK SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13...