W3EG72255S-JD3

White Electronic Designs W3EG72255S-D3 -JD3 -AJD3 PRELIMINARY* 2GB – 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL FEATURES Double-data-rate architecture DDR200, DDR266 and DDR333: JEDEC design specifications Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Dual Rank Power supply: VCC = 2.5V ± 0.2V www.DataSheet4U.com DESCRIPTION The W3EG72255S is a 2x128Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of eighteen 256Mx4 stacks, in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * wThis product is under development, is not qualified or characterized and is subject to change without notice. JEDEC standard 184 pin DIMM package Package height options: JD3: 30.48mm (1.2"), AJD3: 28.70mm (1.13") NOTE: Consult factory for availability of: RoHS compliant products Vendor source control options Industrial temperature option OPERATING FREQUENCIES DDR333 @CL=2.5 Clock Speed CL-tRCD-tRP 166MHz 2.5-3-3 DDR266 @CL=2 133MHz 2-2-2 ...