W3E232M16S-XSTX

White Electronic Designs 2x32Mx16bit DDR SDRAM FEATURES Double-data-rate architecture; two data transfers per clock cycle Data rate = 200, 266, 333, 400 Mbs Package: 66pin TSOP II package 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs(CK and CK#) DLL aligns DQ and DQS transition with CK MRS cycle with address key programs Read latency : 2, 2.5 , 3 (Clock) Burst length (2, 4, or 8) Burst type (sequential & interleave) Auto & Self refresh Modes www.DataSheet4U.com W3E232M16S-XSTX PRELIMINARY* Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (one per byte) DQS edge-aligned with data for READs; centeraligned with data for WRITEs Four internal banks for concurrent operation Data mask (DM) pins for masking write data (one per byte) Programmable IOL/IOH option Auto precharge option Auto Refresh and Self Refresh Modes Commercial, and Industrial Temperature Ranges Organized as 2X32M x 16 * This product is under development, is not qualified +and is subject to change without notice. RoHS Compliant Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle OPERATING FREQUENCIES DDR400 Speed @CL2 Speed @CL2.5 Speed @CL3 * CL = CAS Latency DDR333 133MHz 166MHz — DDR266 133MHz 133MHz — DDR200 100MHz 133MHz — — 166MHz 200MHz FUNCTIONAL BLOCK DIAGRAM CK, CK#, CAS, LDM, UDM RAS#, WE#, UDQS, LDQS CS0#, CKE0 32Mx16 ...