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MT5C1008LL Dataheets PDF



Part Number MT5C1008LL
Manufacturers Austin Semiconductor
Logo Austin Semiconductor
Description 128K x 8 SRAM WITH DUAL CHIP ENABLE ULTRA LOW POWER
Datasheet MT5C1008LL DatasheetMT5C1008LL Datasheet (PDF)

SRAM Austin Semiconductor, Inc. 128K x 8 SRAM WITH DUAL CHIP ENABLE ULTRA LOW POWER AVAILABLE AS MILITARY SPECIFICATIONS •MIL-STD-883, para. 1.2.2 compliant MT5C1008(LL) Ultra Low Power PIN ASSIGNMENT (Top View) 32-Pin DIP (C) NC A16 A14 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 26 27 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE\ A13 A8 A9 A11 OE\ A10 CE1\ I/O7 I/O6 I/O5 I/O4 I/O3 FEATURES • • • • • • • • www.DataSheet4U.com A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND High Sp.

  MT5C1008LL   MT5C1008LL



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SRAM Austin Semiconductor, Inc. 128K x 8 SRAM WITH DUAL CHIP ENABLE ULTRA LOW POWER AVAILABLE AS MILITARY SPECIFICATIONS •MIL-STD-883, para. 1.2.2 compliant MT5C1008(LL) Ultra Low Power PIN ASSIGNMENT (Top View) 32-Pin DIP (C) NC A16 A14 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 26 27 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE\ A13 A8 A9 A11 OE\ A10 CE1\ I/O7 I/O6 I/O5 I/O4 I/O3 FEATURES • • • • • • • • www.DataSheet4U.com A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND High Speed: 30 ns Low active power: 715 mW worst case Low CMOS standby power: 3.3 mW worst case 2.0V data retention, Ultra Low 0.3mW worst case power dissipation Battery backup applications Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE1\, CE2, and OE\ options OPTIONS • Timing 30ns access • Package(s) Ceramic DIP (400 mil) • Temperature Military (-55°C to +125°C) MARKING -30 GENERAL DESCRIPTION C No. 111 The MT5C1008 SRAM is a high-performance CMOS static RAM organized as 131, 072 words by 8 bits, offering low active power and ultra low standby and data retention current levels. Easy memory expansion is provided by an active LOW Chip Enable (CE1\), an active HIGH Chip Enable (CE2), and active Low Output Enable (OE\), and three-state drivers. Writing to the device is accomplished by taking Chip Enable One (CE1\) and Write Enable (WE\) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable One (CE1\) and Output Enable (OE\) LOW while forcing Write Enable (WE\) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1\) HIGH or CE2 LOW), the outputs are disabled (OE\ HIGH), or during a write operation (CE1\ LOW, CE2 HIGH, and WE\ LOW). MIL • Options 2V data retention/very low power LL For more products and information please visit our web site at www.austinsemiconductor.com MT5C1008(LL) Rev. 1.0 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 SRAM Austin Semiconductor, Inc. MT5C1008(LL) Ultra Low Power FUNCTIONAL BLOCK DIAGRAM TRUTH TABLE MODE Power-Down Power-Down Read Write Selected, Outputs Disabled OE\ X X L X H CE1\ H X L L L CE2 X L H H H WE\ X X H L H I/O0 - I/O7 High Z High Z Data Out Data In High Z POWER Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) MT5C1008(LL) Rev. 1.0 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SRAM Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Supply Voltage Range on Vcc to Relative GND ..-0.5V to +7.0V Storage Temperature .............


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