Document
ADC083000 8-Bit, 3 GSPS, High Performance, Low Power A/D Converter
PRELIMINARY
March 2007
ADC083000 8-Bit, 3 GSPS, High Performance, Low Power A/D Converter
General Description
Note: This product is currently in development. - ALL specifications are design targets and are subject to change. The ADC083000 is a single, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 3.4 GSPS. Consuming a typical 1.8 Watts at 3 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters up to Nyquist, producing a high 7.0 Effective Number Of Bits, (ENOB) with a 748 MHz input signal and a 3 GHz sample rate while providing a 10 -18 Bit Error Rate, (BER). The ADC083000 achieves a 3 GSPS sampling rate by utilizing both the rising and falling edge of a 1.5 GHz input clock. Output formatting is offset binary and the LVDS digital outputs are compliant with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V. www.DataSheet4U.com The ADC has a 1:4 demultiplexer that feeds four LVDS buses and reduces the output data rate on each bus to a quarter of the sampling rate. The ADC can be programmed into the 1:2 Output Mode where the data is output on the Dc and Dd channels at the rate of the input clock. The converter typically consumes less than 20 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.
Features
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Internal Sample-and-Hold Single +1.9V ±0.1V Operation Choice of SDR or DDR output clocking 1:2 or 1:4 Selectable Output Demux Clock Phase Adjust for Multiple ADC Synchronization Guaranteed No Missing Codes Serial Interface for Extended Control Adjustment of Input Full-Scale Range and Offset Duty Cycle Corrected Sample Clock Test pattern
Key Specifications
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Resolution Max Conversion Rate Bit Error Rate (BER) ENOB @ 748 MHz Input SNR @ 748 MHz Full Power Bandwidth Power Consumption — Operating — Power Down Mode 8 Bits 3 GSPS (min) 10-18 (typ) 7.0 Bits (typ) 44 dB (typ) 3 GHz (typ) 1.8 W (typ) 20 mW (typ)
Applications
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Direct RF Down Conversion Digital Oscilloscopes Satellite Set-top boxes Communications Systems Test Instrumentation
Ordering Information
Industrial Temperature Range (-40°C < TA < +85°C) ADC083000CIYB ADC08x3000EB NS Package 128-Pin Exposed Pad LQFP Development Board
© 2007 National Semiconductor Corporation
201932
www.national.com
ADC083000
Block Diagram
20193253
Pin Configuration
20193201
Note: The exposed pad on the bottom of the package must be soldered to a ground plane to ensure rated performance.
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2
ADC083000
Pin Descriptions and Equivalent Circuits
Pin Functions Pin No. Symbol Equivalent Circuit Description Output Voltage Aplitude / Serial Interface Clock (Input):LVCMOS Tie this pin high for normal differential DCLK and data amplitude. Ground this pin for a reduced differential output amplitude and reduced power consumption. See Section 1.1.6. When the extended control mode is enabled, this pin functions as the SCLK input which clocks in the serial data.See Section 1.2 for details on the extended control mode. See Section 1.3 for description of the serial interface.
3
OutV / SCLK
4
OutEdge / DDR / SDATA
Edge Select / Double Data Rate / Serial Data (Input):LVCMOS This input sets the output edge of DCLK+ at which the output data transitions. (See Section 1.1.5.2). When this pin is floating or connected to 1/2 the supply voltage, DDR clocking is enabled. When the extended control mode is enabled, this pin functions as the SDATA input. See Section 1.2 for details on the extended control mode. See Section 1.3 for description of the serial interface.
15
DCLK_RST
DCLK Reset (Input):LVCMOS A positive pulse on this pin is used to reset and synchronize the DCLK outs of multiple converters. See Section 1.5 for detailed description. When bit 14 in the Configuration Register (address 1h) is set to 0b, this singleended DCLK_RST pin is selected. Power Down (Input):LVCMOS A logic high on the PD pin puts the entire device into the Power Down Mode. Calibration Cycle Initiate (Input):LVCMOS A minimum 80 input clock cycles logic low followed by a minimum of 80 input clock cycles high on this pin initiates the calibration sequence. See Section 2.4.2 for an overview of self-calibration and Section 2.4.2.2 for a description of on-command calibration. Full Scale Range Select / Extended Control Enable (Input):LVCMOS In non-extended control mode, a logic low on this pin sets the full-scale differential input range to .