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X4283 Dataheets PDF



Part Number X4283
Manufacturers Xicor
Logo Xicor
Description (X4283 / X4285) CPU Supervisor
Datasheet X4283 DatasheetX4283 Datasheet (PDF)

Preliminary Information 128K X4283/85 CPU Supervisor with 128K EEPROM DESCRIPTION 16K x 8 Bit FEATURES • Selectable watchdog timer • Low VCC detection and reset assertion —Four standard reset threshold voltages —Adjust low VCC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V • Low power CMOS —<20µA max standby current, watchdog on —<1µA standby current, watchdog OFF —3mA active current • 128Kbits of EEPROM —64 byte page write mode —Self-timed write cy.

  X4283   X4283


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Preliminary Information 128K X4283/85 CPU Supervisor with 128K EEPROM DESCRIPTION 16K x 8 Bit FEATURES • Selectable watchdog timer • Low VCC detection and reset assertion —Four standard reset threshold voltages —Adjust low VCC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V • Low power CMOS —<20µA max standby current, watchdog on —<1µA standby current, watchdog OFF —3mA active current • 128Kbits of EEPROM —64 byte page write mode —Self-timed write cycle —5ms write cycle time (typical) • Built-in inadvertent write protection —Power-up/power-down protection circuitry —Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512 bytes of EEPROM array with programmable Block Lock™ protection www.DataSheet4U.com • 400kHz 2-wire interface • 2.7V to 5.5V power supply operation • Available packages —8-lead SOIC —8-lead TSSOP BLOCK DIAGRAM Watchdog Transition Detector WP Data Register Command Decode & Control Logic VCC Threshold Reset logic Block Lock Control Protect Logic The X4283/85 combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock protect serial EEPROM memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/ RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the set minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Four industry Watchdog Timer Reset SDA Status Register EEPROM Array 8Kb 4Kb 4Kb RESET (X4283) RESET (X4285) SCL S0 S1 Reset & Watchdog Timebase VCC VTRIP + - Power on and Low Voltage Reset Generation REV 1.17 11/27/00 www.xicor.com Characteristics subject to change without notice. 1 of 22 X4283/85 – Preliminary Information standard Vtrip thresholds are available, however, Xicor’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. The memory portion of the device is a CMOS Serial EEPROM array with Xicor’s Block Lock protection. The array is internally organized as 64 bytes per page. The device features an 2-wire interface and software protocol allowing operation on an 2-wire bus. PIN CONFIGURATION 8-Pin JEDEC SOIC S0 S1 RST/RST VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA 8-Pin TSSOP WP VCC S0 S1 1 2 3 4 8 7 6 5 SCL SDA VSS RST/RST PIN DESCRIPTION Pin (SOIC) 1 2 3 Pin (TSSOP) 3 4 5 Name S0 S1 RESET/ Device Select Input Device Select Input Function RESET Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 250ms. RESET/ RESET goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time out period. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes active on power up and remains active for 250ms after the power supply stabilizes. Ground Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET going active. Serial Clock. The Serial Clock controls the serial bus timing for data input and output. Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the control register. Supply Voltage 4 5 6 7 VSS SDA 6 7 8 8 1 2 SCL WP VCC REV 1.17 11/27/00 www.xicor.com Characteristics subject to change without notice. 2 of 22 X4283/85 – Preliminary Information PRINCIPLES OF OPERATION Power On Reset Application of power to the X4283/85 activates a Power On Reset Circuit that pulls the RESET/RESET pin active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It prevents the processor from operating prior to stabilization of the oscillator. – It allows time for an FPGA to do.


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