Document
®
oH S nd R a e e -Fr Sheet PbData
Co
ant mpli
HI1178
October 25, 2005 FN4115.4
Triple 8-Bit, 40MSPS, RGB, 3-Channel D/A Converter
The HI1178 is a triple 8-bit, high-speed, CMOS D/A converter designed for video band use. It has three separate, 8-bit, pixel inputs, one each for red, green, and blue video data. A single 5.0V power supply and pixel clock input is all that is required to make the device operational. A bias voltage generator is internal. Each channel clock input can be controlled individually, or connected together as one. The HI1178 also has BLANK video control signal.
Features
• Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 8-Bit • Maximum Conversion Speed . . . . . . . . . . . . . . . . . 40MHz • RGB 3-Channel Input/Output • Differential Linearity Error . . . . . . . . . . . . . . . . . +0.3 LSB • Low Power Consumption . . . . . . . . . . . . . . . . . . . .240mW (200Ω Load for 2VP-P Output) • Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . .+5V • Low Glitch Noise • Direct Replacement for Sony CXD1178
Ordering Information
PART NUMBER HI1178JCQ TEMP. RANGE (oC) -40 to 85 PACKAGE 48 Ld MQFP PKG. NO. Q48.12x12-S
Applications
• Digital TV • Graphics Display
Pinout
HI1178 (MQFP) TOP VIEW
DVDD DVDD AVDD AVDD AVDD AVDD VG BO GO GO BO RO
• High Resolution Color Graphics • Video Reconstruction • Instrumentation • Image Processing • I/Q Modulation
www.DataSheet4U.com
R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 G2 G3
1 2 3 4 5 6 7 8 9 10 11 12
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24
RO IREF VREF AVSS VB DVSS DVSS BCK GCK RCK CE BLK
Related Literature
• Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)”
G6 G7
B2 B3
B1
G4
G5
B4 B5
B0
B6
B7
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HI1178 Functional Block Diagram
(LSB) R0 R1 R2 R3 R4 R5 R6 R7 (LSB) G0 G1 G2 G3 G4 G5 G6 G7
1 2 3
2 LSBs CURRENT CELLS
47 48
DVDD DVDD
36 4 5 6 7 8 DECODER CLOCK GENERATOR 43 44 45 46 DECODER LATCHES 6 MSBs CURRENT CELLS 37 27
R0 R0 RCK
AVSS AVDD AVDD AVDD
9 10 11
2 LSBs CURRENT CELLS
38 12 13 14 15 16 DECODER CLOCK GENERATOR 2 LSBs CURRENT CELLS 33 30 (LSB) B0 B1 B2 B3 B4 B5 B6 B7 17 18 19 20 21 22 23 24 DECODER CLOCK GENERATOR + BLK 25 CURRENT CELLS (FOR FULL SCALE) 40 DECODER LATCHES 6 MSBs CURRENT CELLS 41 29 42 31 DECODER LATCHES 6 MSBs CURRENT CELLS 39 28
G0 G0 GCK
AVSS DVSS DVSS
B0 B0 BCK VG VREF IREF
-
34
35
CE
26
BIAS VOLTAGE GENERATOR
32
VB
2
HI1178 Pin Descriptions
PIN NO. 1 to 8 9 to 16 17 to 24 SYMBOL R0 to R7 G0 to G7 B0 to B7
24 DVSS 1
EQUIVALENT CIRCUIT
DVDD
DESCRIPTION Digital input.
25
BLK
DVDD
Blanking pin. No signal at “H” (Output 0V). Output condition at “L”.
25
DVSS
32
VB
DVDD
Connect a capacitor of about 0.1µF.
DVDD
32
+
-
DVSS
27 28 29
RCK CLK
27
DVDD
Clock pin. Moreover all input pins are TTL-CMOS compatible.
BCK
28 29 DVSS
30, 31 33 26
DVSS AVSS CE
DVDD
Digital GND. Analog GND. Chip enable pin. No signal (Output 0V) at “H” and minimizes power consumption.
26
DVSS
3
HI1178 Pin Descriptions
PIN NO. 35 SYMBOL IREF
AVDD AVDD
(Continued) EQUIVALENT CIRCUIT DESCRIPTION Connect a resistance 16 times “16R” that of output resistance value “R”. Set full scale output value.
+ 35 AVDD
34 42
VREF VG
Connect a capacitor of about 0.1µF.
AVSS 34 AVDD
AVSS
42
AVSS
43 to 46 37 39 41 36 38 40
AVDD RO GO BO RO GO BO
36 38 40 AVSS 37 39 41 AVSS AVDD AVDD
Analog VDD . Current output pin. Voltage output can be obtained by connecting a resistance.
Inverted current output pin. Normally dropped to analog GND.
47, 48
DVDD
Digital VDD .
4
HI1178
Absolute Maximum Ratings TA = 25oC
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Input Voltage (VIN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Digital Input Voltage (CLK) . . . . . . . . . . . . . . . . . . . . . 0mA to 15mA (Every Each Channel)
Thermal Information
Thermal Resistance (Typical, Note 1) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range (TSTG) . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (MQFP - Lead Tips Only)
Operating Conditions
Temperature Range (TOPR) . . . . . . . . . . . . . . . . . . . -40oC to 85oC Supply Voltage AVDD , AVSS . . . . . . . . . . . . . . . . . . . . . ..