Document
SPICE Device Model SUM110N04-05H Vishay Siliconix N-Channel 40-V (D-S) 175°C MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics
DESCRIPTION
The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 73146 S-60676Rev. B, 01-May-06 www.vishay.com 1
SPICE Device Model SUM110N04-05H Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static
Gate Threshold Voltage On-State Drain Current
a
Symbol
Test Condition
Simulated Data
3.6 704 0.0046 0.0076 0.0084 0.89
Measured Data
Unit
VGS(th) ID(on)
VDS = VGS, ID = 250 µA VDS = 5 V, VGS = 10 V VGS = 10 V, ID = 30 A
V A 0.0044 Ω
Drain-Source On-State Resistancea
rDS(on)
VGS = 10 V, ID = 30 A, TJ = 125°C VGS = 10 V, ID = 30 A, TJ = 175°C
Forward Voltagea
VSD
IF = 30 A, VGS = 0 V
0.90
V
Dynamic
b
Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Chargec Gate-Source Charge Gate-Drain Chargec
c
Ciss Coss Crss Qg Qgs Qgd VDS = 20 V, VGS = 10 V, ID = 50 A VGS = 0 V, VDS = 25 V, f = 1 MHz
6400 659 268 99 37 21
6700 600 320 95 37 21 nC pF
Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. c. Independent of operating temperature.
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Document Number: 73146 S-60676Rev. B, 01-May-06
SPICE Device Model SUM110N04-05H Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 73146 S-60676Rev. B, 01-May-06
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