HI-6110

HI-6110 November 2006 MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor FEATURES Monolithic CMOS technology 3.3V operation Exceptionally low power On-chip message buffering Selectable master clock frequency Dual differential 1553 bus transceivers Bus Controller / Remote Terminal / Monitor Terminal operating modes Compliant to MIL-STD-1553B Notice 2 and MIL-STD-1760 Stores Management GENERAL DESCRIPTION The HI-6110 is a CMOS integrated circuit implementing the MIL-STD-1553 (1553) data communications protocol between a host processor and a dual redundant 1553 data bus. The single chip architecture has a digital section containing all necessary logic and memory to process and store the command and data words for one complete 1553 message. The analog section includes dual transceivers coupled to the 1553 buses through external current mode transformers. The device is available in an industry standard 64-pin 9 mm square LPCC package, making it the smallest dual redundant 1553 interface product on the market. The HI-6110 may be configured as a Bus Controller (BC), a Remote Terminal (RT), a Monitor Terminal (MT), or a Monitor Terminal with assigned RT address. 16-bit registers store incoming and outgoing Command, Status and Data words. Using two 32-word data FIFOs, the HI-6110 can store the maximum number of 1553 words occurring in any message. For messages with transmitted data words, data may be written in advance or on-the-fly. Received data can be retr...