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LAN91C95 Dataheets PDF



Part Number LAN91C95
Manufacturers SMSC Corporation
Logo SMSC Corporation
Description ISA/PCMCIA Full Duplex Single-Chip Ethernet and Modem Controller
Datasheet LAN91C95 DatasheetLAN91C95 Datasheet (PDF)

LAN91C95 ISA/PCMCIA Full Duplex Single-Chip Ethernet and Modem Controller with RAM FEATURES • • • • • • • • ISA/PCMCIA Single Chip Ethernet Controller With Modem Support 6 Kbytes Built-In RAM Supports IEEE 802.3 (ANSI 8802-3) Ethernet Standards Full Duplex Support Hardware Memory Management Unit Built-In AUI and 10BASE-T Network Interfaces SimultaskingJ - Early Transmit and Early Receive Functions Advanced Power Management Features/Including Magic Packet Frame Control Software Compatible with L.

  LAN91C95   LAN91C95



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LAN91C95 ISA/PCMCIA Full Duplex Single-Chip Ethernet and Modem Controller with RAM FEATURES • • • • • • • • ISA/PCMCIA Single Chip Ethernet Controller With Modem Support 6 Kbytes Built-In RAM Supports IEEE 802.3 (ANSI 8802-3) Ethernet Standards Full Duplex Support Hardware Memory Management Unit Built-In AUI and 10BASE-T Network Interfaces SimultaskingJ - Early Transmit and Early Receive Functions Advanced Power Management Features/Including Magic Packet Frame Control Software Compatible with LAN91C92/ LAN91C94 (in ISA Mode) Configuration Registers Implement Cardbus Multi-Function Specification V3.0 with Backward Compatibility to V2.1 Interfaces Directly to Lucent Technologies and Conexant (formerly Rockwell) Modem Chipsets On-Chip Attribute Memory (CIS) of up to 512 Bytes (On Even Addresses) For Card Configuration Information; Expandable Externally Option for Serial or Parallel EEPROM for CIS • • • • • Optional External Flash Capability for XIP (Execute in Place) Automatic Technology to Detect 10 BASE-T TX/RX Polarity Reversal Low Power CMOS Design Supports Magic Packet Wakeup 128 Pin TQFP Package Bus Interface • • • • • • • • • • • • Direct Interface to ISA and PCMCIA with No Wait States High Impedance Speaker Interface Flexible Bus Interface 16-Bit Data and Control Paths Fast Access Time (40 ns) Pipelined Data Path Handles Block Word Transfers for Any Alignment High Performance Chained ("Back-toBack") Transmit and Receive Flat Memory Structure for Low CPU Overhead Dynamic Memory Allocation Between Transmit and Receive Buffered Architecture, Insensitive to Bus Latencies (No Overruns/Underruns) Supports Boot PROM for Diskless ISA Applications • • • • • Simultasking is a trademark and SMSC is a registered trademark of Standard Microsystems Corporation TABLE OF CONTENTS FEATURES ........................................................................................................................................1 PIN CONFIGURATION.......................................................................................................................3 GENERAL DESCRIPTION .................................................................................................................4 OVERVIEW ........................................................................................................................................4 PIN REQUIREMENTS ........................................................................................................................7 DESCRIPTION OF PIN FUNCTIONS .................................................................................................9 BUFFER TYPES ..............................................................................................................................16 FUNCTIONAL DESCRIPTION..........................................................................................................20 MODEM INTERFACE ......................................................................


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