SY100EP451L

SY10/100EP451L 3.3V ECL 6-Bit Differential Register with Master Reset General Description The SY10/100EP451L is a 6-bit fully differential register with common clock and single-ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have an internal 75k Ω pull-down resistor. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to < VEE +1.2V, the clamp will override and force the output to a default state. The positive transition of CLK (pin 4) will latch the registers. Master Reset (MR) HIGH will asynchronously reset all registers forcing Q outputs to go LOW. Datasheets and support documentation can be found on Micrel’s web site at: www.micrel.com. Features 450ps typical propagation delay Maximum frequency > 3.0GHz typical Asynchronous Master Reset 20ps skew within device, 35ps skew device-to-device PECL mode operating range: – VCC = 3.0V to 3.6V with VEE = 0V NECL mode operating range: – VCC = 0V with VEE = –3.0V to –3.6V Open input default state Safety clamp on inputs Available in 32-pin TQFP Applications High Speed Logic Wireless Communication Systems Data Communication Systems www.DataSheet4U.com Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com March 2007 M9999-030507-A hbwhelp@micre...