SY100S324

Micrel, Inc. NOT RECOMMENDED FOR NEW DESIGNS LOW POWER HEX TTL-to-ECL TRANSLATOR SY100S324 SY100S324 FEATURES DESCRIPTION s Max. propagation delay of 1.4ns s IEE min. of –70mA s Industry standard 100K ECL levels s Extended supply voltage option: VEE = –4.2V to –5.5V s Differential outputs s Voltage and temperature compensation for improved noise immunity s Internal 75kΩ input pull-down resistors s Twice as fast as Fairchild’s 324 s Function and pinout compatible with Fairchild F100K s Available in 28-pin PLCC package The SY100S324 is a hex translator designed to convert TTL logic levels to 100K ECL levels. The inputs are TTL compatible with differential outputs that can either be used as an inverting/non-inverting translator or as differential line drivers. A common Enable (E), when LOW, holds all inverting outputs HIGH and holds all noninverting outputs LOW. When used in the differential mode, due to its high common mode rejection, it overcomes voltage gradients between the TTL and ECL ground systems. The VEE and VTTL power may be applied in either order. BLOCK DIAGRAM E D0 D1 D2 D3 D4 D5 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 PIN NAMES Pin D0–D5 E Q0–Q5 Q0–Q5 VEES VTTL VCCA Function Data Inputs Enable Inputs Data Outputs Complementary Data Outputs VEE Substrate TTL VCC Power Supply VCCO for ECL Outputs M9999-042307 [email protected] or (408) 955-1690 1 Rev.: I Amendment: /0 Issue Date: April 2007 Micrel, Inc. SY100S324 PACKAGE/ORDERING INFORMATION Q1 Q1 Q0...