SY100S302

Micrel, Inc. QUINT 2-INPUT OR/NOR GATE SY100S302 SY100S302 FEATURES DESCRIPTION s Max. propagation delay of 700ps s IEE min. of –45mA s Industry standard 100K ECL levels s Extended supply voltage option: VEE = –4.2V to –5.5V s Voltage and temperature compensation for improved noise immunity s Internal 75kΩ input pull-down resistors s 50% faster than Fairchild 300K s Function and pinout compatible with Fairchild F100K s Available in 28-pin PLCC package The SY100S302 offers five 2-input OR/NOR gates designed for use in high-performance ECL systems. The five gates are controlled by a common Enable signal. All inputs have 75kΩ pull-down resistors and all outputs are buffered. BLOCK DIAGRAM D1a D2a D1b D2b D1c D2c D1d D2d D1e D2e E Oa Oa Ob Ob Oc Oc Od Od Oe Oe PIN NAMES Pin Dna – Dne E Oa – Oe Oa – Oe VEES VCCA Function Data Inputs (n-1...5) Enable Input Data Outputs Complementary Data Outputs VEE Substrate VCCO for ECL Outputs M9999-042307 [email protected] or (408) 955-1690 1 Rev.: I Amendment: /0 Issue Date: April 2007 Micrel, Inc. SY100S302 PACKAGE/ORDERING INFORMATION D2a D1a Oa VEES Oa Ob Ob D1b D2b VEE VEES E D1c D2c 11 10 9 8 7 6 5 12 4 13 3 14 Top View 2 15 PLCC J28-1 1 16 28 17 27 18 26 19 20 21 22 23 24 25 Oc Oc VCCA VCC VCC Od Od D1d D2d D1e VEES D2e Oe Oe 28-Pin PLCC (J28-1) Ordering Information Part Number SY100S302JC SY100S302JCTR(1) SY100S302JZ(2) Package Type J28-1 J28-1 J28-1 SY100S302JZTR(1, 2) J28-1 Operating Range Com...