DS26502

DS26502 T1/E1/J1/64KCC BITS Element www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26502 is a building-integrated timing§ G.703 2048kHz Synchronization Interface supply (BITS) clock-recovery element. It also Compliant functions as a basic T1/E1 transceiver. The § G.703 64kHz Centralized (Option A) and receiver portion can recover a clock from T1, Codirectional Timing Interface Compliant E1, 64kHz composite clock (64KCC), and § G.703 Appendix II 64kHz and 6312kHz 6312kHz synchronization timing interfaces. In Japanese Synchronization Interface T1 and E1 modes, the Synchronization Status Compliant § Interfaces to Standard T1/J1 (1.544MHz) and Message (SSM) can also be recovered. The transmit portion can directly interface to T1, E1, E1 (2.048MHz) § Interface to CMI-Coded T1/J1 and E1 or 64KCC synchronization interfaces as well as § Short- and Long-Haul Line Interface source the SSM in T1 and E1 modes. The § Transmit and Receive T1 and E1 SSM DS26502 can translate between any of the Messages with Message Validation supported inbound synchronization clock rates to § T1/E1 Jitter Attenuator with Bypass Mode any supported outbound rate. A separate output § Fully Independent Transmit and Receive is provided to source a 6312kHz clock. The Functionality device is controlled through a parallel, serial, or www.DataSheet4U.com hardware controller port. § Internal Software-Selectable Receive- and Transmit-Side Termination for 75Ω/100Ω/110Ω/120Ω T1, E1, and Composite Clock Interface...