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NB100LVEP56 Dataheets PDF



Part Number NB100LVEP56
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description ECL Dual Differential 2:1 Multiplexer
Datasheet NB100LVEP56 DatasheetNB100LVEP56 Datasheet (PDF)

2.5 V/3.3 V ECL DUAL Differential 2:1 Multiplexer NB100LVEP56 Description The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or differential data signals. The device features both individual and common select inputs to address both data path and random logic applications. Common and individual selects can accept both LVECL and LVCMOS input voltage levels. Multiple VBB pins are provided. The VBB pin, a.

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2.5 V/3.3 V ECL DUAL Differential 2:1 Multiplexer NB100LVEP56 Description The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or differential data signals. The device features both individual and common select inputs to address both data path and random logic applications. Common and individual selects can accept both LVECL and LVCMOS input voltage levels. Multiple VBB pins are provided. The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input operation, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Features • Maximum Input Clock Frequency > 2.5 GHz Typical • Maximum Input Data Rate > 2.5 Gb/s Typical • 525 ps Typical Propagation Delays • Low Profile QFN Package • PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −2.375 V to −3.8 V • Separate, Common Select, and Individual Select (Compatible with ECL and CMOS Input Voltage Levels) • Q Output Will Default LOW with Inputs Open or at VEE • Multiple VBB Outputs • These Devices are Pb−Free and are RoHS Compliant www.onsemi.com 24 1 QFN24 MN SUFFIX CASE 485L MARKING DIAGRAM* 24 1 N100 VP56 ALYWG G A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping† NB100LVEP56MNG NB100LVEP56MNR2G QFN24 (Pb−Free) QFN24 (Pb−Free) 92 Units / Tube 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 1 May, 2021 − Rev. 12 Publication Order Number: NB100LVEP56/D NB100LVEP56 Table 1. PIN FUNCTION DESCRIPTION ÁÁÁÁÁÁÁÁÁÁ Pin No. QFN Name 3,9,18,19, VCC 20 Default I/O State − − 15,24 VEE − − 6,12 4 5 VBB0, VBB1 D0a D0a − ECL Input ECL Input − Low High 7 D0b ECL Input Low 8 D0b ECL Input High 10 D1a ECL Input Low 11 D1a ECL Input High 13 D1b ECL Input Low 14 D1b ECL Input High 2 Q0 ECL Output − 1 Q0 ECL Output − 17 Q1 ECL Output − 16 Q1 ECL Output − 23 SEL0 ECL, CMOS Low Input 22 COM_SEL ECL, CMOS Low Input 21 SEL1 ECL, CMOS Low Input − EP − Description Positive Supply Voltage. All VCC Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. Negative Supply Voltage. All VEE Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. ECL Reference Voltage Output Noninverted Differential Data a Input to MUX 0. Internal 75 kW to VEE. Inverted Differential Data a Input to MUX 0. Internal 75 kW to VEE and 37 kW to VCC. Noninverted Differential Data b Input to MUX 0. Internal 75 kW to VEE. Inverted Differential Data b Input to MUX 0. Internal 75 kW to VEE and 37 kW to VCC. Noninverted Differential Data a Input to MUX 1. Internal 75 kW to VEE. Inverted Differential Data a Input to MUX 1. Internal 75 kW to VEE and 37 kW to VCC. Noninverted Differential Data b Input to MUX 1. Internal 75 kW to VEE. Inverted Differential Data b Input to MUX 1. Internal 75 kW to VEE and 37 kW to VCC. Noninverted Differential Output MUX 0. Typically Terminated with 50 W to VTT = VCC − 2.0 V. Inverted Differential Output MUX 0. Typically Terminated with 50 W to VTT = VCC − 2.0 V. Noninverted Differential Output MUX 1. Typically Terminated with 50 W to VTT = VCC − 2.0 V. Inverted Differential Output MUX 1. Typically Terminated with 50 W to VTT = VCC − 2.0 V. Noninverted Differential Select Input to MUX 0. Internal 75 kW to VEE. Noninverted Differential Common Select Input to Both MUX. Internal 75 kW to VEE. Noninverted Differential Select Input to MUX 1. Internal 75 kW to VEE. Exposed Pad. The exposed pad (EP) on the package bottom must be attached to a heat−sinking conduit. The exposed pad may only be electrically connected to VEE. www.onsemi.com 2 NB100LVEP56 0 0 D0a R1 R2 1 D0a Q0 R1 D0b R1 R2 D0b R1 D1a R1 R2 1 D1a R1 Q0 SEL0 R1 COM_SEL R1 SEL1 R1 Q1 Table 2. TRUTH TABLE SEL0 X L L H H SEL1 X L H H L COM_SEL H L L L L Q0, Q0 a b b a a Q1, Q1 a b a a b D1b R1 R2 D1b R1 Q1 VCC VEE Figure 1. Logic Diagram COM VEE SEL0 SEL SEL1 VCC VCC 24 23 22 21 20 19 Exposed Pad (EP) Q0 1 Q0 2 18 VCC 17 Q1 VCC 3 D0a 4 D0a 5 NB100LVEP56 16 Q1 15 VEE 14 D1b VBB0 6 13 D1b 7 8 9 10 11 12 D0b D0b VCC D1a D1a VBB1 Figure 2. QFN−24 Lead Pinout (Top View) Table 3. ATTRIBUTES C.


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