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NB100LVEP222 Dataheets PDF



Part Number NB100LVEP222
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description 1:15 Differential ECL/PECL /1 /2 Clock Driver
Datasheet NB100LVEP222 DatasheetNB100LVEP222 Datasheet (PDF)

NB100LVEP222 2.5 V/3.3 V 1:15 Differential ECL/PECL ÷1/÷2 Clock Driver The NB100LVEP222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be used in a differential configuration or single−ended (with VBB output reference bypassed and connected to the unused input of a pair). Either of two fully differential clock inputs may be selected. Each of the four output banks of 2, 3, 4, and 6 differential pairs may be.

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NB100LVEP222 2.5 V/3.3 V 1:15 Differential ECL/PECL ÷1/÷2 Clock Driver The NB100LVEP222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be used in a differential configuration or single−ended (with VBB output reference bypassed and connected to the unused input of a pair). Either of two fully differential clock inputs may be selected. Each of the four output banks of 2, 3, 4, and 6 differential pairs may be independently configured to fanout 1X or 1/2X of the input frequency. When the output banks are configured with the B1 mode, data can also be distributed. The LVEP222 specifically guarantees low output to output skew. Optimal design, layout, and processing minimize skew within a device and from lot to lot. This device is an improved version of the MC100LVE222 with higher speed capability and reduced skew. The fsel pins and CLK_Sel pin are asynchronous control inputs. Any changes may cause indeterminate output states requiring an MR pulse to resynchronize any 1/2X outputs (See Figure 3). Unused output pairs should be left unterminated (open) to reduce power and switching noise. The NB100LVEP222, as with most ECL devices, can be operated from a positive VCC/VCC0 supply in LVPECL mode. This allows the LVEP222 to be used for high performance clock distribution in +2.5/3.3 V systems. In a PECL environment series or Thevenin line, terminations are typically used as they require no additional power www.DataSheet4U.com supplies. For more information on using PECL, designers should refer to Application Note AN1406/D. For a SPICE model, refer to Application Note AN1560/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended LVPECL input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC/VCC0 via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Single−ended CLK input operation is limited to a VCC/VCC0 ≥ 3.0 V in LVPECL mode, or VEE v −3.0 V in NECL mode. http://onsemi.com MARKING DIAGRAM* 52−LEAD LQFP THERMALLY ENHANCED CASE 848H FA SUFFIX A WL YY WW G NB100 LVEP222 AWLYYWWG 52 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional information, see Application Note AND8002/D ORDERING INFORMATION Device NB100LVEP222FA Package LQFP−52 Shipping † 160 Units/Tray NB100LVEP222FAR2 LQFP−52 1500/Tape & Reel NB100LVEP222FAG LQFP−52 (Pb−Free) 160 Units/Tray • • • • • 20 ps Output−to−Output Skew 85 ps Part−to−Part Skew Selectable 1x or 1/2x Frequency Outputs LVPECL Mode Operating Range: VCC/VCC0 = 2.375 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC/VCC0 = 0 V with VEE = −2.375 V to −3.8 V Internal Input Pulldown Resistors NB100LVEP222FARG LQFP−52 1500/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. • • Performance Upgrade to ON Semiconductor’s MC100LVE222 • VBB Output • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 1 October, 2005− Rev. 9 Publication Order Number: NB100LVEP222/D NB100LVEP222 VCC0 VCC0 VCC0 27 26 25 24 23 22 21 Qc0 Qc0 Qc1 Qc1 Qc2 Qc2 Qc3 Qc3 NC 29 VCC0 Qb2 Qb2 Qb1 Qb1 Qb0 Qb0 VCC0 Qa1 Qa1 Qa0 Qa0 VCC0 39 40 41 42 43 44 45 46 47 48 49 50 51 52 1 38 37 36 35 34 33 32 31 30 NC 28 Qd0 Qd0 Qd1 Qd1 Qd2 Qd2 Qd3 Qd3 Qd4 Qd4 Qd5 Qd5 VCC0 NB100LVEP222 20 19 18 17 16 15 14 2 3 4 5 6 7 8 9 10 11 12 13 CLK0 CLK0 MR CLK1 CLK1 fseld L VBB CLK_Sel fsela fselb All VCC, VCC0, and VEE pins must be externally connected to appropriate Power Supply to guarantee proper operation.VCC pin internally connected to VCC0 pins. The thermally conductive exposed pad on package bottom (see package case drawing) must be attached to a heat−sinking conduit. This exposed pad is electrically connected to VEE internally. Figure 1. 52−Lead LQFP Pinout (Top View) PIN DESCRIPTION PIN CLK0*, CLK0** CLK1*, CLK1** CLK_Sel* MR* Qa0:1, Qa0:1 Qb0:2, Qb0:2 Qc0:3, Qc0:3 Qd0:5, Qd0:5 fseln* VBB VCC, VCC0 VEE*** NC FUNCTION ECL Differential Input Clock ECL Differential Input Clock ECL Clock Select ECL Master Reset ECL Differential Outputs ECL Differential Outputs ECL Differential Outputs ECL Differential Outputs ECL 1 or 2 Select Reference Voltage Output Positive Supply, VCC = VCC0 Negative Supply No Connect Input MR CLK_Sel fseln FUNCTION TABLE Function H Reset CLK1 ÷2 fselc VCC Active CLK0 ÷1 * Pins will default LOW when left open. ** Pins will default HIGH when left open. *** The therm.


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