Input to LVDS Fanout Buffer/Translator
NB6N11S
3.3 V 1:2 AnyLevelE Input to LVDS Fanout Buffer / Translator
Description The NB6N11S is a differential 1:2 Clock...
Description
NB6N11S
3.3 V 1:2 AnyLevelE Input to LVDS Fanout Buffer / Translator
Description The NB6N11S is a differential 1:2 Clock or Data Receiver and will
accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical copies of Clock or Data will be distributed, operating up to 2.0 GHz or 2.5 Gb/s, respectively. As such, the NB6N11S is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or Data distribution applications.
The NB6N11S has a wide input common mode range from GND + 50 mV to VCC − 50 mV. Combined with the 50 W internal termination resistors at the inputs, the NB6N11S is ideal for translating a variety of differential or single−ended Clock or Data signals to 350 mV typical LVDS output levels.
The NB6N11S is functionally equivalent to the EP11, LVEP11, SG11 or 7L11M devices and is offered in a small, 3 mm X 3 mm, 16−QFN package. Application notes, models, and support documentation are available at www.onsemi.com.
The NB6N11S is a member of the ECLinPS MAX™ family of high performance products.
Features
Maximum Input Clock Frequency > 2.0 GHz Maximum Input Data Rate > 2.5 Gb/s 1 ps Maximum of RMS Clock Jitter Typically 10 ps of Data Dependent Jitter 380 ps Typical Propagation Delay 120 ps Typical Rise and Fall Times Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and
SG Devices
These are Pb−Free Devices
www.onsemi.com
1
QFN−16 MN SUFFIX CASE 485G
MARKING DIAGRAM*
16 1
NB...
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