MC10162

MC10162 Binary to 1-8 Decoder (High) The MC10162 is designed to convert three lines of input data to a one–of–eight output. The selected output will be high while all other outputs are low. The enable inputs, when either or both are high, force all outputs low. The MC10162 is a true parallel decoder. No series gating is used internally, eliminating unequal delay times found in other decoders. This device is ideally suited for demultiplexer applications. One of the two enable inputs is used as the data input, while the other is used as a data enable input. A complete mux/demux operation on 16 bits for data distribution is illustrated in Figure 1 of the MC10161 data sheet. PD = 315 ns typ/pkg (No Load) tpd = 4.0 ns typ tr, tf = 2.0 ns typ (20%–80%) LOGIC DIAGRAM E0Ą2 E1Ą15 6ĄQ0 5ĄQ1 4ĄQ2 www.DataSheet4U.com 3ĄQ3 13ĄQ4 BĄ9 12ĄQ5 11ĄQ6 CĄ14 10ĄQ7 http://onsemi.com MARKING DIAGRAMS 16 CDIP–16 L SUFFIX CASE 620 1 16 PDIP–16 P SUFFIX CASE 648 1 1 PLCC–20 FN SUFFIX CASE 775 10162 AWLYYWW MC10162P AWLYYWW MC10162L AWLYYWW AĄ7 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week DIP PIN ASSIGNMENT VCC1 E0 Q3 Q2 Q1 Q0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 E1 C Q4 Q5 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 TRUTH TABLE INPUTS E0 L L L L L L L L H X E1 L L L L L L L L X H C L L L L H H H H X X B L L H H L L H H X X A L H L H L H L H X X Q0 H L L L L L L L L L Q1 L H L L L L L L L L Q2 L L H L L L L L L L OUTPUTS Q3 L L L H L L L L L L Q4 L L L L H L L L L L Q5 L L...