Document
3.3 V LVTTL/LVCMOS to LVPECL Translator
MC100EPT622
Description The MC100EPT622 is a 10−Bit LVTTL/LVCMOS to LVPECL
translator. Because LVPECL (Positive ECL) levels are used only +3.3 V and ground are required. The device has an OR−ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs (ENTTL). If the inputs are left open, they will default to the enable state. The device design has been optimized for low channel−to−channel skew.
Features
• 450 ps Typical Propagation Delay • Maximum Frequency > 1.5 GHz Typical • PECL Mode • Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V • PNP LVTTL Inputs for Minimal Loading • Q Output Will Default HIGH with Inputs Open • The 100 Series Contains Temperature Compensation • These Devices are Pb−Free, Halogen Free and are RoHS Compliant
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MARKING DIAGRAMS*
LQFP−32 FA SUFFIX CASE 561AB
MC100 EPT622 AWLYYWWG
32
1
1 32
QFN32 MN SUFFIX CASE 488AM
1
MC100 EPT622 AWLYYWWG
G
A WL YY WW G or G
= Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to Application Note AND8002/D.
Table 1. TRUTH TABLE
ENPECL ENTTL
D
Q
H
X
H
H
H
X
L
L
X
H
H
H
X
H
L
L
L
L
X
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
1
March, 2021 − Rev. 7
Publication Order Number: MC100EPT622/D
D5 D6 D7 D8 D9 ENTTL ENPECL VEE
12345678
MC100EPT622
VCCO D4 D3 D2 VEE D1 D0 VCCO
ENPECL ENTTL D0
25
26
27
28
29
30
31
32
24 23 22 21 20 19 18 17
12
MC100EPT622
13
14
15
16
VCCO
D1
Q0
Q1
D2
Q2
VCCO
D3
Q3
Q4 LVCMOS/TTL D4
VCCO D5
11
10
9
Q0 Q1 Q2 Q3 Q4 LVPECL Q5
VCCO Q9 Q8 Q7 VCC Q6 Q5 VCCO
Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. 32−Lead LQFP Pinout (Top View) Exposed Pad
VCCO D4 D3 D2 VEE D1 D0 VCCO
(EP)
32 31 30 29 28 27 26 25
D5 1 D6 2
24 VCCO 23 Q0
D7 3
22 Q1
D8 4
21 Q2
D9 5 ENTTL 6
20 VCCO 19 Q3
ENPECL VEE
7
18 Q4
8
17 VCCO
9 10 11 12 13 14 15 16
VCCO Q9 Q8 Q7 VCC Q6 Q5 VCCO Figure 3. 32−Lead QFN Pinout (Top View)
D6 Q6
D7 Q7
D8 Q8
D9 Q9
Figure 2. Logic Symbol
Table 1. PIN DESCRIPTION
Pin
Function
D0:9
Data Input (TTL)
Q0:9
Data Outputs (PECL)
ENTTL
Enable Control (TTL)
ENPECL Enable Control (PECL)
VCC, VCCO VEE EP
Positive Supply
Ground
The exposed pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out of the package. THe exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to VEE.
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MC100EPT622
Table 2. ATTRIBUTES
Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection
Human Body Model Machine Model Charged Device Model
Characteristics
Moisture Sensitivity, Indefinite Time Out of Drypack
LQFP−32 QFN−32
Flammability Rating Oxygen Index: 28 to 34
Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Value N/A N/A
> 2 kV > 150 V > 2 kV Pb−Free Pkg Level 2 Level 1
UL 94 V−0 @ 0.125 in 596 Devices
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
Power Supply
VI
Input Voltage
Iout
Output Current
VEE = 0 V VEE = 0 V Continuous Surge
VI ≤ VCC
5
V
5 to 0
V
50
mA
100
mA
TA
Operating Temperature Range
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
32 LQFP 32 LQFP
−40 to +85
−65 to +150
80 55
°C °C °C/W °C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
qJA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
32 LQFP
QFN−32 QFN−32
12 to 17
31 27
°C/W
°C/W °C/W
qJC
Thermal Resistance (Junction−to−Case)
2S2P
QFN−32
12
°C/W
Tsol
Wave Solder
265
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
Table 4. TTL INPUT DC CHARACTERISTICS (VCC = 3.3 V, GND= 0.0 V, TA = −40°C to 85°C)
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
IIH
Input HIGH Current
IIHH
Input HIGH Current MAX
IIL
Input LOW Current
VIK
Input Clamp Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIN = 2.7 V VIN = VCC VIN = 0.5 V IIN = −18 mA
25
mA
100
mA
−0.6
mA
−1.2
−0.9
V
2.0
V
0.8
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm.
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MC100EPT622
Table 5. PECL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND= 0.0 V, TA = −40°C to 85°C
Symbol
Characteristic
.