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CAT24C05 Dataheets PDF



Part Number CAT24C05
Manufacturers Catalyst Semiconductor
Logo Catalyst Semiconductor
Description I2C Serial EEPROM
Datasheet CAT24C05 DatasheetCAT24C05 Datasheet (PDF)

CAT24C03/05 FEATURES 2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection DEVICE DESCRIPTION The CAT24C03/CAT24C05 is a 2-kb/4-kb CMOS Serial EEPROM device organized internally as 16/32 pages of 16 bytes each, for a total of 256x8/512x8 bits. These devices support both Standard (100kHz) as well as Fast (400kHz) I2C protocol. Data is written by providing a starting address, then loading 1 to 16 contiguous bytes into a Page Write Buffer, and then writing all data to non-volatile me.

  CAT24C05   CAT24C05


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CAT24C03/05 FEATURES 2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection DEVICE DESCRIPTION The CAT24C03/CAT24C05 is a 2-kb/4-kb CMOS Serial EEPROM device organized internally as 16/32 pages of 16 bytes each, for a total of 256x8/512x8 bits. These devices support both Standard (100kHz) as well as Fast (400kHz) I2C protocol. Data is written by providing a starting address, then loading 1 to 16 contiguous bytes into a Page Write Buffer, and then writing all data to non-volatile memory in one internal write cycle. Data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count. Write operations can be inhibited for upper half of memory by taking the WP pin High. External address pins make it possible to address up to eight CAT24C03 or four CAT24C05 devices on the same bus. ■ Supports Standard and Fast I2C Protocol ■ 1.8 V to 5.5 V Supply Voltage Range ■ 16-Byte Page Write Buffer ■ Hardware Write Protection for upper half of memory ■ Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA). ■ Low power CMOS technology ■ 1,000,000 program/erase cycles ■ 100 year data retention ■ Industrial temperature range ■ RoHS-compliant 8-lead PDIP, SOIC, and TSSOP, 8-pad TDFN and 5-lead TSOT-23 packages. For Ordering Information details, see page 17. www.DataSheet4U.com PIN CONFIGURATION PDIP (L) SOIC (W) TSSOP (Y) TDFN (VP2) CAT24C05 / 03 NC / A0 A1 / A1 A2 / A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA SCL VSS SDA 1 2 3 4 VCC 5 WP FUNCTIONAL SYMBOL VCC TSOT-23 (TD) SCL A2, A1, A0 WP CAT24C03 CAT24C05 SDA For the location of Pin 1, please consult the corresponding package drawing. PIN FUNCTIONS A0, A1, A2 SDA SCL WP VCC VSS NC Device Address Inputs Serial Data Input/Output Serial Clock Input Write Protect Input Power Supply Ground No Connect * Catalyst carries the I2C protocol under a license from the Philips Corporation. VSS © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1116, Rev. B CAT24C03/05 ABSOLUTE MAXIMUM RATINGS(1) Storage Temperature Voltage on Any Pin with Respect to Ground(2) RELIABILITY CHARACTERISTICS(3) Symbol NEND(4) TDR Parameter Endurance Data Retention Min 1,000,000 100 Units Program/ Erase Cycles Years -65°C to +150°C -0.5 V to +6.5 V D.C. OPERATING CHARACTERISTICS VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. Symbol ICCR ICCW ISB IL VIL VIH VOL1 VOL2 Parameter Read Current Write Current Standby Current I/O Pin Leakage Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA VCC < 2.5 V, IOL = 1.0 mA Test Conditions Read, fSCL = 400 kHz Write, fSCL = 400 kHz All I/O Pins at GND or VCC Pin at GND or VCC -0.5 Min Max 1 1 1 1 VCC x 0.3 Units mA mA μA μA V V V V VCC x 0.7 VCC + 0.5 0.4 0.2 PIN IMPEDANCE CHARACTERISTICS VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. Symbol CIN(3) CIN(3) IWP(5) Parameter SDA I/O Pin Capacitance Input Capacitance (other pins) WP Input Current Conditions VIN = 0 V VIN = 0 V VIN < VIH, VCC = 5.5 V VIN < VIH, VCC = 3.3 V VIN < VIH, VCC = 1.8 V VIN > VIH Note: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Page Mode, VCC = 5 V, 25°C (5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Max 8 6 200 150 100 1 Units pF pF μA Doc. No. 1116, Rev. B 2 CAT24C03/05 A.C. CHARACTERISTICS(1) VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C. Standard Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF(2) tSU:STO tBUF tAA tDH Ti(2) tSU:WP tHD:WP tWR tPU(2, 3) Note: (1) Test conditions according to “A.C. Test Conditions” table. (2) Tested initially and after a design or process change that affects this parameter. (3).


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