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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low-Voltage CMOS Octal D-Type Flip-Flop Flow Through Pinout
With 5V-Tolerant Inputs and Outputs (3-State, Non-Inverting)
MC74LCX574
The MC74LCX574 is a high performance, non–inverting octal D–type flip–flop operating from a 2.7 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5V allows MC74LCX574 inputs to be safely driven from 5V devices. The MC74LCX574 consists of 8 edge–triggered flip–flops with individual D–type inputs and 3–state true outputs. The buffered clock and buffered Output Enable (OE) are common to all flip–flops. The eight flip–flops will store the state of individual D inputs that meet the setup and hold time requirements on the LOW–to–HIGH Clock (CP) transition. With the OE LOW, the contents of the eight flip–flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. The OE input level does not affect the operation of the flip–flops. The LCX574 flow through design facilitates easy PC board layout.
LOW–VOLTAGE CMOS OCTAL D–TYPE FLIP–FLOP
20 1
DW SUFFIX PLASTIC SOIC CASE 751D–04
• • • • • • • •
Designed for 2.7 to 3.6V VCC Operation 5V Tolerant — Interface Capability With 5V TTL Logic Supports Live Insertion and Withdrawal
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20 1
M SUFFIX PLASTIC SOIC EIAJ CASE 967–01
IOFF Specification Guarantees High Impedance When VCC = 0V LVTTL Compatible LVCMOS Compatible 24mA Balanced Output Sink and Source Capability
20
Near Zero Static Supply Current in All Three Logic States (10µA) Substantially Reduces System Power Requirements • Latchup Performance Exceeds 500mA
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SD SUFFIX PLASTIC SSOP CASE 940C–03
• ESD Performance: Human Body Model >2000V; Machine Model >200V
20 1
DT SUFFIX PLASTIC TSSOP CASE 948E–02
Pinout: 20–Lead (Top View)
VCC 20 O0 19 O1 18 O2 17 O3 16 O4 15 O5 14 O6 13 O7 12 CP 11
PIN NAMES
Pins OE CP D0–D7 O0–O7 Function Output Enable Input Clock Pulse Input Data Inputs 3–State Outputs
1 OE
2 D0
3 D1
4 D2
5 D3
6 D4
7 D5
8 D6
9 D7
10 GND
9/95
© Motorola, Inc. 1996
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REV 2
MC74LCX574
LOGIC DIAGRAM
OE CP 1 11 nCP Q D 18 Q D 17 Q D 16 Q D nCP Q D 14 Q D nCP Q D 12 Q D O7 13 O6 O5 15 O4 O3 O2 O1 19 O0
2 D0
3 D1
nCP
4 D2
nCP
5 D3
nCP
6 D4
7 D5
nCP
8 D6
9 D7
nCP
INPUTS OE L L L H H H CP ↑ ↑ ↑ ↑ ↑ ↑ Dn l h X X l h
INTERNAL LATCHES Q L H NC NC L H
OUTPUTS On L H NC Z Z Z OPERATING MODE Load and Read Register Hold and Read Register Hold and Disable Outputs Load Internal Register and Disable Outputs
H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Low–to–High Clock Transition; L = Low Voltage Level; l = Low Voltage Level One Setup Time Prior to the Low–to–High Clock Transition; NC = No Change; X = High or Low Voltage Level and Transitions are Acceptable; Z = High Impedance State; ↑ = Low–to–High Transition; ↑ = Not.