MC10EP51

www.DataSheet4U.com MC10EP51, MC100EP51 3.3V / 5V ECL D Flip−Flop with Reset and Differential Clock Description The MC10/100EP51 is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip−flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the CLK input will be biased at VCC/2. The 100 Series contains temperature compensation. Features http://onsemi.com MARKING DIAGRAMS* 8 1 SOIC−8 D SUFFIX CASE 751 1 8 HEP51 ALYW G 1 8 KEP51 ALYW G 8 1 TSSOP−8 DT SUFFIX CASE 948R 8 HP51 ALYWG G 8 KP51 ALYWG G 350 ps Typical Propagation Delay Maximum Frequency > 3 GHz Typical PECL Mode Operating Range: VCC = 3.0 V to 5.5 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V Open Input Default State Safety Clamp on Inputs Pb−Free Packages are Available with VEE = 0 V 1 1 DFN8 MN SUFFIX CASE 506AA H K 5S 3N M = MC10 = MC100 = MC10 = MC100 = Date Code 1 5S MG G 4 1 A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot m...