MC10E160

www.DataSheet4U.com MOTOROLA SEMICONDUCTOR TECHNICAL DATA 12ĆBit Parity Generator/Checker MC10E160 MC100E160 The MC10E/100E160 is a 12-bit parity generator/checker. The Q output is HIGH when an odd number of inputs are HIGH. A HIGH on the Enable input (EN) forces the Q output LOW. The E160 also features an output register. Multiplexers direct the register input, giving the option of holding present data by asserting HOLD LOW, or of shifting data in through the S-IN pin by asserting SHIFT HIGH. The output register itself is clocked by a positive edge on CLK1 or CLK2 (or both). A HIGH on the reset pin (R) overrides to force the Y output LOW. 12-BIT PARITY GENERATOR/CHECKER Provides Odd-HIGH Parity of 12 Inputs Shiftable Output Register with Hold 900ps Max. D to Q/Q Output Enable Asynchronous Register Reset Dual Clocks Extended 100E VEE Range of – 4.2V to – 5.46V 75kΩ Input Pulldown Resistors Pinout: 28-Lead PLCC (Top View) D4 25 D5 D6 D7 26 27 28 1 2 3 4 5 6 7 8 9 10 11 D3 24 D2 23 D1 22 D0 21 EN 20 VCCO 19 18 17 16 15 14 13 12 Q Q VCC Y Y VCCO NC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 EN HOLD Function Data Inputs Serial Data Input Enable, active LOW Hold, active LOW Shift, active HIGH Clock Inputs Reset Inputs Direct Output Register Output S-IN SHIFT CLK1 CLK2 R FN SUFFIX PLASTIC PACKAGE CASE 776-02 LOGIC DIAGRAM VEE D8 D9 D10 Q D11 HOLD S-IN SHIFT CLK1 CLK2 R * All VCC and VCCO pins are tied together on the die. 0 MUX 1 SEL 0 MUX 1 SEL D R Y Y ...