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74VCXH16374 Dataheets PDF



Part Number 74VCXH16374
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description Low-Voltage 1.8/2.5/3.3V 16-Bit D-Type Flip-Flop
Datasheet 74VCXH16374 Datasheet74VCXH16374 Datasheet (PDF)

www.DataSheet4U.com 74VCXH16374 Low−Voltage 1.8/2.5/3.3V 16−Bit D−Type Flip−Flop With 3.6 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The 74VCXH16374 is an advanced performance, non−inverting 16−bit D−type flip−flop. It is designed for very high−speed, very low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The VCXH16374 is byte controlled, with each byte functioning identically, but independently. Each byte has separate Output Enable and Clock Pulse inputs. These control pins ca.

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www.DataSheet4U.com 74VCXH16374 Low−Voltage 1.8/2.5/3.3V 16−Bit D−Type Flip−Flop With 3.6 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The 74VCXH16374 is an advanced performance, non−inverting 16−bit D−type flip−flop. It is designed for very high−speed, very low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The VCXH16374 is byte controlled, with each byte functioning identically, but independently. Each byte has separate Output Enable and Clock Pulse inputs. These control pins can be tied together for full 16−bit operation. When operating at 2.5 V (or 1.8 V) the part is designed to tolerate voltages it may encounter on either inputs or outputs when interfacing to 3.3 V busses. It is guaranteed to be overvoltage tolerant to 3.6V. The 74VCXH16374 consists of 16 edge−triggered flip−flops with individual D−type inputs and 3.6 V−tolerant 3−state outputs. The clocks (CPn) and Output Enables (OEn) are common to all flip−flops within the respective byte. The flip−flops will store the state of individual D inputs that meet the setup and hold time requirements on the LOW−to−HIGH Clock (CP) transition. With the OE LOW, the contents of the flip−flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. The OE input level does not affect the operation of the flip−flops. The data inputs include active bushold circuitry, eliminating the need for external pullup resistors to hold unused or floating inputs at a valid logic state. Features http://onsemi.com MARKING DIAGRAM 48 48 1 VCXH16374 AWLYYWW TSSOP−48 DT SUFFIX CASE 1201 A WL YY WW 1 = Assembly Location = Wafer Lot = Year = Work Week PIN NAMES Pins OEn CPn D0−D15 O0−O15 Function Output Enable Inputs Clock Pulse Inputs Inputs Outputs • Designed for Low Voltage Operation: VCC = 1.65 V − 3.6 V • 3.6 V Tolerant Inputs and Outputs • High Speed Operation: 3.0 ns max for 3.0 V to 3.6V • • • • • • • • 3.9 ns max for 2.3 V to 2.7V 7.8 ns max for 1.65 V to 1.95V Static Drive: ±24 mA Drive at 3.0 V ±18 mA Drive at 2.3 V ±6 mA Drive at 1.65 V Supports Live Insertion and Withdrawal Includes Active Bushold to Hold Unused or Floating Inputs at a Valid Logic State IOFF Specification Guarantees High Impedance When VCC = 0 V* Near Zero Static Supply Current in All Three Logic States (20 mA) Substantially Reduces System Power Requirements Latchup Performance Exceeds ±250 mA @ 125°C ESD Performance: Human Body Model >2000 V Machine Model >200 V All Devices in Package TSSOP are Inherently Pb−Free** ORDERING INFORMATION Device 74VCXH16374DT 74VCXH16374DTR Package TSSOP (Pb−Free) TSSOP (Pb−Free) Shipping † 39 / Rail 2500 / Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *To ensure the outputs activate in the 3−state condition, the output enable pins should be connected to VCC through a pullup resistor. The value of the resistor is determined by the current sinking capability of the output connected to the OE pin. **For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 5 1 Publication Order Number: 74VCXH16374/D 74VCXH16374 OE1 1 O0 2 O1 3 GND 4 O2 5 O3 6 VCC 7 O4 8 O5 9 GND 10 O6 11 O7 12 O8 13 O9 14 GND 15 O10 16 O11 17 VCC 18 O12 19 O13 20 GND 21 O14 22 O15 23 OE2 24 48 CP1 47 D0 46 D1 45 GND 44 D2 43 D3 42 VCC 41 D4 40 D5 39 GND 38 D6 37 D7 36 D8 35 D9 34 GND 33 D10 32 D11 31 VCC 30 D12 29 D13 28 GND 27 D14 26 D15 25 CP2 D7 37 D6 38 D5 40 nCP D nCP D nCP D Q D4 41 nCP D Q D3 43 nCP D Q 6 O3 D11 32 nCP D nCP D nCP D nCP D nCP D Q 17 O11 D2 44 nCP D Q 5 O2 D10 33 nCP D Q 16 O10 D1 46 nCP D Q 3 O1 D9 35 nCP D Q 14 O9 D0 47 OE1 CP1 1 48 nCP D Q 2 O0 OE2 CP2 D8 24 25 36 nCP D Q 13 O8 8 O4 D12 30 Q 19 O12 9 O5 D13 29 Q 20 O13 Q 11 O6 D14 27 Q 22 O14 Q 12 O7 D15 26 Q 23 O15 Figure 1. 48−Lead Pinout (Top View) Figure 2. Logic Diagram OE1 48 CP1 25 CP2 24 OE2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1 EN1 EN2 EN3 EN4 1 1∇ 2∇ 1 1 3∇ 1 4∇ 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 Figure 3. IEC Logic Diagram http://onsemi.com 2 74VCXH16374 TRUTH TABLE Inputs CP1 ↑ ↑ X X OE1 L L L H D0:7 H L X X Outputs O0:7 H L O0 Z CP2 ↑ ↑ X X Inputs OE2 L L L H D8:15 H L X X Outputs O8:15 H L O0 Z H = High Voltage Level L = Low Voltage Level Z = High Impedance State ↑ = Low−to−High Transition X = High or Low Voltage Level and Transitions Are Acceptable, for ICC reasons, DO NOT FLOAT Inputs. O0 = No Change. ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO ICC IGND TSTG DC Supply Voltage DC Input Voltage DC Output Voltage Parameter Value −0.5 to +4.6 −0.5 ≤ VI ≤ +4.6 −0.5 .


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