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74VCX16240 Dataheets PDF



Part Number 74VCX16240
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description Low-Voltage 1.8/2.5/3.3V 16-Bit Buffer
Datasheet 74VCX16240 Datasheet74VCX16240 Datasheet (PDF)

www.DataSheet4U.com 74VCX16240 Low−Voltage 1.8/2.5/3.3V 16−Bit Buffer With 3.6 V−Tolerant Inputs and Outputs (3−State, Inverting) The 74VCX16240 is an advanced performance, inverting 16−bit buffer. It is designed for very high−speed, very low−power operation in 1.8 V, 2.5 V or 3.3 V systems. When operating at 2.5 V (or 1.8 V) the part is designed to tolerate voltages it may encounter on either inputs or outputs when interfacing to 3.3 V busses. It is guaranteed to be over−voltage tolerant to 3..

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www.DataSheet4U.com 74VCX16240 Low−Voltage 1.8/2.5/3.3V 16−Bit Buffer With 3.6 V−Tolerant Inputs and Outputs (3−State, Inverting) The 74VCX16240 is an advanced performance, inverting 16−bit buffer. It is designed for very high−speed, very low−power operation in 1.8 V, 2.5 V or 3.3 V systems. When operating at 2.5 V (or 1.8 V) the part is designed to tolerate voltages it may encounter on either inputs or outputs when interfacing to 3.3 V busses. It is guaranteed to be over−voltage tolerant to 3.6 V. The 74VCX16240 is nibble controlled with each nibble functioning identically, but independently. The control pins may be tied together to obtain full 16−bit operation. The 3−state outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are on. When OEn is HIGH, the outputs are in the high impedance state. Features http://onsemi.com MARKING DIAGRAM 48 48 1 VCX16240 AWLYYWW TSSOP−48 DT SUFFIX CASE 1201 A WL YY WW 1 = Assembly Location = Wafer Lot = Year = Work Week • Designed for Low Voltage Operation: VCC = 1.65 V − 3.6 V • 3.6V Tolerant Inputs and Outputs • High Speed Operation: 2.5 ns max for 3.0 V to 3.6 V • • • • • • • 3.0 ns max for 2.3 V to 2.7 V 6.0 ns max for 1.65 V to 1.95 V Static Drive: ±24 mA Drive at 3.0 V ±18 mA Drive at 2.3 V ±6 mA Drive at 1.65 V Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0 V Near Zero Static Supply Current in All Three Logic States (20 mA) Substantially Reduces System Power Requirements Latchup Performance Exceeds ±250 mA @ 125°C ESD Performance: Human Body Model >2000 V; Machine Model >200 V All Devices in Package TSSOP are Inherently Pb−Free* ORDERING INFORMATION Device 74VCX16240DT 74VCX16240DTR Package TSSOP (Pb−Free) TSSOP (Pb−Free) Shipping † 39 / Rail 2500 / Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 5 1 Publication Order Number: 74VCX16240/D 74VCX16240 OE1 1 O0 2 O1 3 GND 4 O2 5 O3 6 VCC 7 O4 8 O5 9 GND 10 O6 11 O7 12 O8 13 O9 14 GND 15 O10 16 O11 17 VCC 18 O12 19 O13 20 GND 21 O14 22 O15 23 OE4 24 48 OE2 47 D0 46 D1 45 GND 44 D2 43 D3 42 VCC 41 D4 40 D5 39 GND 38 D6 37 D7 36 D8 35 D9 34 GND 33 D10 32 D11 31 VCC 30 D12 29 D13 28 GND 27 D14 26 D15 25 OE3 D0:3 O0:3 D8:11 O8:11 OE1 OE2 1 48 OE3 OE4 25 24 D4:7 O4:7 D12:15 O12:15 One of Four Figure 2. Logic Diagram OE1 48 OE2 25 OE3 24 OE4 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1 1 1 1 EN1 EN2 EN3 EN4 1 1∇ 2 3 5 6 8 9 11 2∇ 3∇ 12 13 14 16 4∇ 17 19 20 22 23 Figure 1. 48−Lead Pinout (Top View) O0 O1 O2 O3 O4 O5 O6.


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