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STP95N04 STD95N04
N-CHANNEL 40V - 5.4mΩ - 80A - DPAK - TO-220 STripFET™ Power MOSFET
General features
Type STD95N04 STP95N04
■ ■
VDSS 40V 40V
RDS(on) <6.5mΩ <6.5mΩ
ID 80A 80A
Pw 110W 110W
3 1
1 2 3
STANDARD THRESHOLD DRIVE 100% AVALANCHE TESTED
DPAK
TO-220
Description
This N-Channel enhancement mode MOSFET is the latest refinement of STMicroelectronic unique “Single Feature Size™“ strip-based process with less critical aligment steps and therefore a remarkable manufacturing reproducibility. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and low gate charge.
Internal schematic diagram
Applications
■ ■
HIGH CURRENT,SWITCHING APPLICATION AUTOMOTIVE
Order codes
Sales Type STD95N04 STP95N04
Marking D95N04 P95N04
Package DPAK TO-220
Packaging TAPE & REEL TUBE
December 2005
Rev 3 1/14
www.st.com 14
1 Electrical ratings
STD95N04 - STP95N04
1
Table 1.
Electrical ratings
Absolute maximum ratings
Parameter Drain-source Voltage (VGS=0) Gate-Source Voltage Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Value 40 ± 20 80 65 320 110 0.73 8 400 -55 to 175 Unit V V A A A W W/°C V/ns mJ °C
Symbol VDS VGS ID Note 1 ID IDM Note 2 PTOT
dv/dt Note 3 Peak Diode Recovery voltage slope EAS Note 4 Tj Tstg Single Pulse Avalanche Energy Operating Junction Temperature Storage Temperature
Table 2.
Thermal data
TO-220 DPAK 1.36 62.5 -300 -50 -°C/W °C/W °C/W °C
Rthj-case Rthj-a Rthj-pcb Note 5 Tl
Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose
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STD95N04 - STP95N04
2 Electrical characteristics
2
Electrical characteristics
(TCASE = 25 °C unless otherwise specified)
Table 3.
Symbol V(BR)DSS IDSS
On/off states
Parameter Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate Body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-Source On Resistance Test Conditions ID = 250µA, V GS= 0 VDS = Max Rating, VDS = Max Rating,Tc = 125°C VGS = ±20V VDS= VGS, ID = 250µA VGS= 10V, ID= 40A 2 5.4 Min. 40 10 100
±200
Typ.
Max.
Unit V µA µA nA V mΩ
IGSS VGS(th) RDS(on)
4 6.5
Table 4.
Symbol gfs Note 6 Ciss Coss Crss Qg Qgs Qgd
Dynamic
Parameter Forward Transconductance Test Conditions VDS =25V, ID=40A Min. Typ. 100 2200 580 40 40 11 8 54 Max. Unit S pF pF pF nC nC nC
Input Capacitance VDS =25V, f=1 MHz, V GS=0 Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD=20V, ID = 80A VGS =10V (see Figure 13)
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2 Electrical characteristics
STD95N04 - STP95N04
Table 5.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on Delay Time Rise Time Test Conditions VDD=20V, ID= 40A, RG=4.7Ω, VGS=10V (see Figure 12) VDD=20V, ID= 40A, RG=4.7Ω, VGS=10V (see Figure 12) Min. Typ. 15 50 Max. Unit ns ns
Turn-off Delay Time FallTime
40 15
ns ns
Table 6.
Symbol ISD ISDM Note 2 VSDNote 6 trr Qrr IRRM
Source drain diode
Parameter Source-drain Current Source-drain Current (pulsed) Forward on Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD=80A, V GS=0 ISD=80A, di/dt = 100A/µs, VDD=30V, Tj=150°C 45 60 2.8 Test Conditions Min. Typ. Max. 80 320 1.5 Unit A A V ns nC A
(1) Current limited by package (2) Pulse width limited by safe operating area (3) ISD ≤ 80 A, di/dt ≤ 400A/µs, VDS ≤ V(BR)DSS, Tj≤ Tjmax (4) Starting Tj=25°C, Id =40A, Vdd=30V (5) When mounted on 1inch² FR4 2Oz Cu board (6)Pulsed: pulse duration = 300µs, duty cycle 1.5%
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STD95N04 - STP95N04
2 Electrical characteristics
2.1
Electrical characteristics (curves)
Safe Operating Area Figure 2. Thermal Impedance
Figure 1.
Figure 3.
Output Characteristics
Figure 4.
Transfer Characteristics
Figure 5.
Static Drain-source on Resistance
Figure 6.
Normalized BVDSS vs Temperature
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2 Electrical characteristics
STD95N04 - STP95N04
Capacitance Variations
Figure 7.
Gate Charge vs Gate-source Voltage Figure 8.
Figure 9.
Normalized Gate Threshold Voltage Figure 10. Normalized on Resistance vs vs Temperature Temperature
Figure 11. Source-drain Diode Forward Characteristics
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STD95N04 - STP95N04
3 Test circuits
3
Test circuits
Figure 13. Gate Charge Test Circuit
Figure 12. Switching Times Test Circuit for Resistive Load
Figure 14. Test Circuit for Inductive Load Switching and Diode Recovery Times
Figure 15. Unclamped Inductive Load Test Circuit
Figure 16. Unclamped Inductive Waveform
Figure 17. Switching Time Waveform
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3 Test circuits
STD95N04 - STP95N04
Figure 18. Diode Reverse Recovery Waveform
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STD95N04 - STP95N04
4 Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free secon.