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ZL30226/7/8 4/8/16 Port IMA/TC PHY Device for xDSL
Data Sheet Features
IMA • • • • • Up to 16 xDSL links & up to 8 IMA groups with 1 to 16 links/IMA group1 Supports symmetrical & asymmetrical operation CTC (common transmit) & ITC (independent transmit) clocking modes Pre-processing of RX ICP (IMA control protocol) cells IMA layer & per link statistics and alarms for performance monitoring with MIB support • Ordering Information ZL30226/GA ZL30227/GA ZL30228/GA 384 Pin PBGA 384 Pin PBGA 384 Pin PBGA
March 2004
-40°C to +85 °C HEC (header error control) verification & generation, error detection, filler cell filtering (IMA) and idle/unassigned cell filtering (TC) TC layer statistics and error counts i.e. HEC errors with MIB support
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TC and UNI • Supports mixed-mode operation: links not assigned to an IMA group can be used in TC mode ATM framing using cell delineation Standards Compliant • • ATM Forum - IMA 1.1 (AF-PHY-0086.001) & backwards compatible with IMA 1.0 ITU G.804 cell mapping & ITU I.432 cell delineation
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1. ZL30226 supports up to 4 serial links with maximum 4 groups to be used - groups 0, 1, 2, 3. ZL30227 supports up to 8 serial links ZL30228 supports up to 16 serial links
RX External Static RAM
TDM Ring
RX Utopia Level 2 BUS TX
Rx Utopia FIFo
Internal IMA Processors (1 per group)
TDM Ring Control S/P
xDSL
Utopia I/F CTRL
Cell Delineator CD Circuits (1 per link)
xDSL
P/S Tx Utopia FIFo
Transmission Convergence
TDM Ring Control
xDSL Serial TDM Ports (1 per link, up to 10Mb/s per link)
TC Circuits (1 per link) Processor I/F
TDM Ring
Figure 1 - ZL30226/7/8 Block Diagram with Built-in IMA functions for up to 8 IMA Groups over 4/8/16 links 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30226/7/8
General • • • • • • • • • • Supports TDM serial links up to 10 Mb/s for xDSL Single chip ATM IMA & TC processor Versatile TDM interface for most popular xDSL chipsets Up to 6 ZL30226/7/8 devices can be spanned using a TDM ring supporting 32 links
Data Sheet
Provides 8 & 16-bit UTOPIA Level 1 & 2 compatible MPHY Interface (ZL30226/7/8 slaved to ATM device) 16-bit microprocessor interface for Intel or Motorola JTAG test support 2.5 V core, 3.3 V I/O with 5 V tolerant inputs 384 pin PGBA with 1.0 mm pitch balls ZL30226, ZL30227 and ZL30228 share the same product package and pin-out configuration
Applications
Provides cost effective solutions to implement IMA and/or TC functions over xDSL transport facilities in broadband access networks. Typical applications are for trunking or subscriber access in: • • • Integrated access devices Access multiplexers Next-generation DLC
Overview
The ZL30226, ZL30227 and ZL30228 form a family of similar devices, differing mainly in the maximum number of serial links, and are collectively referred to as ZL30226/7/8. It should be noted throughout this document whenever reference is made to the number of serial links that the ZL30228 offers a maximum of 16 serial links (links 15:0), while the ZL30227 offers a maximum of 8 serial links (links 14, 12, 10, 8, 6, 4, 2 and 0), and the ZL30226 offers a maximum of 4 serial links (links 12, 8, 4 and 0). Pin and register compatibility has been maintained to offer interchangeability. Note: When creating IMA groups for ZL30226 the groups 0,1,2 and 3 should be used.
Description
The ZL30226/7/8 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications. In the ZL30226/7/8 architecture, up to 16 physical and independent serial links can be terminated through the utilization of off-the-shelf xDSL chip sets. The ZL30226/7/8 can provide up to 10 Mb/s per link data rates for TDM serial transmissions for xDSL applications. The ZL30226/7/8 device provides ATM system designers with a flexible architecture when implementing ATM access over existing line interfaces, allowing a migration towards ATM service technology. The ZL30226/7/8 device is compliant with the ATM FORUM IMA specifications for controlling IMA groups of up to 16 lines in a single chip. The ZL30226/7/8 can be configured to operate in different modes to facilitate the implementation of the IMA function at both CPE and Central Office sites. For systems targeting ATM over DSL with IMA and TC operating simultaneously, the ZL30226/7/8 device provides the ideal architecture and capabilities. The device provides up to 8 internal IMA processors and allows for bandwidth scaleability through the use of the UTOPIA MPHY, Level 1 and Level 2 specification at rates up to 52 Mhz. The implementation of IMA as per AF-PHY-0086.001 Inverse Multiplexing for ATM (IMA) Specification Version 1.1 is divided into hardware and software functions. Hardware functions are implemented in the ZL30226/7/8 device and software functions are implemented by the IMA Co.