ZL30107

www.DataSheet4U.com ZL30107 GbE Line Card Synchronizer Shortform Data Sheet March 2007 A full Data Sheet is available to qualified customers. To register, please send an email to [email protected]. Ordering Information ZL30107GGG 64 Pin CABGA Trays ZL30107GGG2 64 Pin CABGA* Trays *Pb Free Tin/Silver/Copper -40oC to +85oC Configurable to accept a 25 MHz input reference Automatic entry into Asynchronous Holdover mode when all input references fail Input reference is manually selectable through the serial (SPI) interface Hitless input reference switching Lock indicator pin Input reference status monitors Programmable loop bandwidth of 14 Hz, 28 Hz, or 890 Hz Features Single chip low cost solution for synchronizing an Ethernet PHY to a standard telecom clock Generates an IEEE 802.3 jitter compliant 25 MHz Gigabit Ethernet output clock Supports three modes of operation: Asynchronous Freerun, Synchronous, and Asynchronous Holdover Defaults in Asynchronous Freerun mode In Asynchronous Freerun mode, the DPLL generates an output clock with a frequency accuracy equal to frequency accuracy of the external crystal oscillator (XO) or a low cost crystal (XTAL) In Synchronous mode, the DPLL automatically synchronizes to one of a pre-defined set of frequencies including 2 kHz, 8 kHz, 64 kHz, 1.544 MHz, 2.048 MHz, 6.48 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz, 38.88 MHz, 77.76 MHz. Applications Ethernet Line Cards Supporting Synchronous Transmission X1...