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2 Mbit / 4 Mbit SPI Serial Flash
SST25LF020A / SST25LF040A
SST25LF020A / 040A2Mb / 4Mb Serial Peripheral Interface (SPI) flash memory
Data Sheet
FEATURES:
• Single 3.0-3.6V Read and Write Operations • Serial Interface Architecture – SPI Compatible: Mode 0 and Mode 3 • 33 MHz Max Clock Frequency • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Read Current: 7 mA (typical) – Standby Current: 8 µA (typical) • Flexible Erase Capability – Uniform 4 KByte sectors – Uniform 32 KByte overlay blocks • Fast Erase and Byte-Program: – Chip-Erase Time: 70 ms (typical) – Sector- or Block-Erase Time: 18 ms (typical) – Byte-Program Time: 14 µs (typical) • Auto Address Increment (AAI) Programming – Decrease total chip programming time over Byte-Program operations • End-of-Write Detection – Software Status • Hold Pin (HOLD#) – Suspends a serial sequence to the memory without deselecting the device • Write Protection (WP#) – Enables/Disables the Lock-Down function of the status register • Software Write Protection – Write protection through Block-Protection bits in status register • Temperature Range – Commercial: 0°C to +70°C – Industrial: -40°C to +85°C – Extended: -20°C to +85°C • Packages Available – 8-lead SOIC 150 mil body width for SST25LF020A – 8-lead SOIC 200 mil body width for SST25LF040A – 8-contact WSON (5mm x 6mm) • All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
SST’s serial flash family features a four-wire, SPI-compatible interface that allows for a low pin-count package occupying less board space and ultimately lowering total system costs. SST25LF020A/040A SPI serial flash memories are manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The splitgate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST25LF020A/040A devices significantly improve performance, while lowering power consumption. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST25LF020A/040A devices operate with a single 3.03.6V power supply. The SST25LF020A devices are offered in an 8-lead SOIC 150 mil body width (SA) package. The SST25LF040A devices are offered in an 8-lead SOIC 200 mil body width (S2A) package. All densities are offered in the 8-contact WSON package. See Figure 1 for the pin assignments.
©2006 Silicon Storage Technology, Inc. S71242-05-000 1/06 1
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
Address Buffers and Latches
X - Decoder
SuperFlash Memory
Y - Decoder
Control Logic
I/O Buffers and Data Latches
Serial Interface
1242 B1.0
CE#
SCK
SI
SO
WP#
HOLD#
©2006 Silicon Storage Technology, Inc.
S71242-05-000
1/06
2
2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A
Data Sheet
PIN DESCRIPTION
CE# SO WP# VSS
1 2
8 7
VDD HOLD# SCK SI
CE# SO WP# VSS
1
8
VDD HOLD# SCK SI
2
7
Top View
3 4 6 5
1242 08-soic P1.0 3
Top View
6
4
5 1242 08-wson P2.0
8-LEAD SOIC FIGURE 1: PIN ASSIGNMENTS TABLE 1: PIN DESCRIPTION
Symbol Pin Name SCK Serial Clock Functions
8-CONTACT WSON
To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence. The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. To temporarily stop serial communication with SPI flash memory without resetting the device. To provide power supply (3.0-3.6V).
T1.0 1242
SI SO CE# WP# HOLD# VDD VSS
Serial Data Input Serial Data Output Chip Enable Write Protect Hold Power Supply Ground
©2006 Silicon Storage Technology, Inc.
S71242-05-000
1/06
3
2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A
Data Sheet
PRODUCT IDENTIFICATION
TABLE 2: PRODUCT IDENTIFICATION
Address Manufacturer’s ID Device ID SST25LF020A SST25LF040A 00001H 00001H 43H 44H
T2.0 1242
DEVICE OPERATION
The SST25LF020A/040A is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol. The SPI bus consist of f.