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EB632 Dataheets PDF



Part Number EB632
Manufacturers Freescale Semiconductor
Logo Freescale Semiconductor
Description Functional Differences
Datasheet EB632 DatasheetEB632 Datasheet (PDF)

www.DataSheet4U.com Freescale Semiconductor Engineering Bulletin EB632 Rev. 2, 1/2005 Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M) 1 Introduction CONTENTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A Introduction..1 Summary of Differences ..2 SIU 3 Reset....

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www.DataSheet4U.com Freescale Semiconductor Engineering Bulletin EB632 Rev. 2, 1/2005 Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M) 1 Introduction CONTENTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A Introduction.........................................................1 Summary of Differences .....................................2 SIU ......................................................................3 Reset....................................................................6 Boot.....................................................................9 Clock System ....................................................14 Memory Map ....................................................22 ORx in UPM Mode...........................................22 HDI16 ...............................................................22 DMA Transfer Code Definitions ......................36 Interrupt System................................................36 Debugging.........................................................36 EFCOP ..............................................................37 CPM ..................................................................37 Errata.................................................................56 Bootloader Program ..........................................82 This document describes the differences between MSC8101 mask set 2K42A and MSC8103 mask set 2K87M. These differences include: • System Interface Unit (SIU) changes: — Internal Memory Map Register (IMMR) MASKNUM field value — Addition of the Internal Memory Map Mirror Register (IMMMR) Reset changes: — Modes — Hard Reset Configuration Word (HRCW) layout Boot source changes Clock changes — Clock scheme — System Clock Mode Register (SCMR) — Addition of the CLKODIS field to the System Clock Control Register (SCCR) — Clock modes — CLKIN to CLKOUT delay change — Maximum clock frequencies change Memory map addition of IMMMR ORx in UPM mode, bit 27 functionality difference Host interface (HDI16) changes Direct memory access (DMA) controller transfer code (TC) definitions • • • • • • • © Freescale Semiconductor, Inc., 2002, 2005. All rights reserved. Summary of Differences • • • • • • Interrupt system changes: — CPM Low Interrupt Priority Registers (SCPRR_L and SCPRR_L_EXT) definitions — Assignment of interrupt vector 44 to transmission convergence (TC) layer request Debugging system changes: — JTAG ID — EOnCE Status Register (ESR) values Removal of Enhanced Filter Coprocessor (EFCOP) support Communications processor module (CPM) changes: — RISC Controller Configuration Register (RCCR) — Dual-port RAM — Addition of ROM-based inverse multiplexing for ATM (IMA) microcode — Addition of TC layer functionality to the time-slot assigner (TSA) with support through FCC2 — Addition of new MCC host commands Errata New bootloader program 2 Summary of Differences Table 1. Difference Summary for MSC8101 Mask Set 2K42A and MSC8103 Mask Set 2K87M Module Function Internal Memory Map Register (IMMR) Internal Memory Map Mirror Register (IMMMR) Supported modes Hardware reset configuration word Table 1 lists a summary of the differences between MSC8101 mask set 2K42A and MSC8103 mask set 2K87M. MSC8101 Mask Set 2K42A MASKNUM bit field = 0x02 Not supported Host reset and hardware reset Seventeen fields defined From host (HDI16) or external memory (system bus) Clock scheme configures SPLL PDF, SPLL MF, and Bus DF Defines seven fields Defines one field (DFBRG) Two valid modes A function of frequency DLL-enabled mode is not supported and designs must use a zero-delay clock buffer. — BCLK/CLKOUT/SCLK = 68.75 MHz CPMCLK = 137.5 MHz DSPCLK = 275 MHz MSC8103 Mask Set 2K87M MASKNUM bit field = 0x12 Added Host reset, hardware reset, and reduced reset Eighteen fields defined--software watchdog disable (SWDIS) bit added From host (HDI16), external memory (system bus), or serial EPROM (I2C interface) Clock scheme configures SPLL PDF, SPLL MF, Bus DF, CPM DF, Core DF, CPLL PDF, and CPLL MF Defines eight fields Defines two fields (CLKODIS and DFBRG) Twenty-seven valid modes Not a function of frequency To enable the DLL, the zero-delay clock buffer recommended for the 2K42A mask set must be placed in PLL-bypass mode or replaced. For clock modes 5, 6, 46, and 57, apply offsets to DLL-disabled timing. BCLK/CLKOUT/SCLK = 100 MHz CPMCLK = 200 MHz DSPCLK = 300 MHz System Interface Unit (SIU) Reset Boot Boot sources supported Clock Clock Scheme System Clock Mode Register (SCMR) System Clock Control Register (SCCR) Clock modes CLKIN-to-CLKOUT delay Enabling the DLL Disabling the DLL Maximum clock frequencies Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2 2 Freescale Semiconductor SIU Table 1. Difference Summary for MSC8101 Mask Set 2K42A and MSC8103 Mask Set 2K87M (Continued) Module Memory Map IMMMR SCCR Memory Controller Host Port (HDI16) Direct Memory Access (DMA) controller Interrupts ORx in.


EB622 EB632 B5094


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