PI6C48533-01

www.DataSheet4U.com PI6C48533-01 3.3V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer Features Pin-to-pin compatible to ICS8533-01 Maximum operation frequency: 800MHz 4 pair of differential LVPECL outputs Selectable differential CLK and PCLK inputs CLK, nCLK pair accepts LVDS, LVPECL, LVHSTL, SSTL and HCSL input level PCLK, nPCLK pair supports LVPECL, CML and SSTL input level Output Skew: 100ps (maximum) Part-to-part skew: 150ps (maximum) Propagation delay: 2ns (maximum) 3.3V power supply Operating Temperature: -40oC to 85oC Packaging (Pb-free & Green avaliable): -20-pin TSSOP (L) Description The PI6C48533-01 is a high-performance low-skew LVPECL fanout buffer. PI6C48533-01 features two selectable differential inputs and translates to four LVPECL ultra-low jitter outputs. The inputs can also be configured to single-ended with external resistor bias circuit. The CLK input accepts LPECL or LVDS or LVHSTL or SSTL or HCSL signals, and PCLK input accepts LVPECL or SSTL or CML signals. The outputs are synchronized with input clock during asynchronous assertion/deassertion of CLK_EN pin. PI6C48533-01 is ideal for differential to LVPECL translations and/or LVPECL clock distribution. Typical clock translation and distribution applications are data-communications and telecommunications. Block Diagram CLK_EN D LE nCLK Pin Diagram VEE CLK_EN CLK_SEL CLK 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q Q0 nQ0 VCC Q1 nQ1 CLK 0 1 PCLK nPCLK ...