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Integrated Circuit Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
FEATURES
• 5 differential 3.3V LVPECL outputs • Selectable CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum output frequency up to 650MHz • Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input • Output skew: 35ps (maximum) • Part-to-part skew: 150ps (maximum) • Propagation delay: 2.1ns (maximum) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS85304-01 is a low skew, high performance 1-to-5 Differential-to-3.3V LVPECL fanout HiPerClockS™ buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85304-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
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Guaranteed output and part-to-part skew characteristics make the ICS85304-01 ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_EN D Q LE CLK nCLK PCLK nPCLK
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC CLK_EN VCC nPCLK PCLK VEE nCLK CLK CLK_SEL VCC
00 11
Q0 nQ0 Q1 nQ1
CLK_SEL Q2 nQ2 Q3 nQ3 Q4 nQ4
ICS85304-01
20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm Package Body G Package Top View
85304AG-01
www.icst.com/products/hiperclocks.html
1
REV. B JULY 13, 2001
Integrated Circuit Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Type Description Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Positive supply pins. Connect to 3.3V. Clock select input. When HIGH, selects PCLK, nPCLK inputs. Pulldown When LOW, selects CLK, nCLK inputs. LVTTL / LVCMOS interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Negative supply pin. Connect to ground. Pulldown Non-inver ting differential LVPECL clock input. Pullup
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 6 7, 8 9, 10 11, 18, 20 12 13 14 15 16 17 Name Q0, nQ0 Q1, nQ1 Q2, nQ2 Q3, nQ3 Q4, nQ4 VCC CLK_SEL CLK nCLK VEE PCLK nPCLK Output Output Output Output Output Power Input Input Input Power Input Input
Inver ting differential LVPECL clock input. Synchronizing clock enable. When HIGH, clock outputs follow clock 19 CLK_EN Input Pullup input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVTTL / LVCMOS interface levels. NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter CLK, nCLK CIN Input Capacitance PCLK, nPCLK CLK_EN, CLK_SEL Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum 4 4 4 51 51 Units pF pF pF KΩ KΩ
RPULLUP RPULLDOWN
85304AG-01
www.icst.com/products/hiperclocks.html
2
REV. B JULY 13, 2001
Integrated Circuit Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Inputs Outputs Selected Source CLK, nCLK PCLK, nPCLK CLK, nCLK Q0 thru Q4 Disabled; LOW Disabled; LOW Enabled nQ0 thru nQ4 Disabled; HIGH Disabled; HIGH Enabled
TABLE 3A. CONTROL INPUT FUNCTION TABLE
CLK_EN 0 0 1 CLK_SEL 0 1 0
1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B.
Disabled
nCLK, nPCLK CLK, PCLK
Enabled
CLK_EN
nQ0 - nQ4 Q0 - Q4
FIGURE 1 - CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK or CLK 0 1 0 1 Biased; NOTE 1 nPCLK or nPCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 LOW HIGH LOW HIGH HIGH Outputs Q0 thru Q4 nQ0 thru nQ4 HIGH LOW HIGH LOW LOW Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting
Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information section on page 8, Figure 8, which discusses wiring the differential input to accept single ended levels.
85304AG-01
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