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54ACT373 Dataheets PDF



Part Number 54ACT373
Manufacturers National Semiconductor
Logo National Semiconductor
Description Octal Transparent Latch
Datasheet 54ACT373 Datasheet54ACT373 Datasheet (PDF)

www.DataSheet4U.com 54AC373 • 54ACT373 Octal Transparent Latch with TRI-STATE Outputs August 1998 54AC373 • 54ACT373 Octal Transparent Latch with TRI-STATE ® Outputs General Description The ’AC/’ACT373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When O.

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www.DataSheet4U.com 54AC373 • 54ACT373 Octal Transparent Latch with TRI-STATE Outputs August 1998 54AC373 • 54ACT373 Octal Transparent Latch with TRI-STATE ® Outputs General Description The ’AC/’ACT373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. Features n n n n n n ICC and IOZ reduced by 50% Eight latches in a single package TRI-STATE outputs for bus interfacing Outputs source/sink 24 mA ’ACT373 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) — ’AC373: 5962-87555 — ’ACT373: 5962-87556 Logic Symbols IEEE/IEC DS100329-1 DS100329-2 Pin Names D0–D7 LE OE O0–O7 Description Data Inputs Latch Enable Input Output Enable Input TRI-STATE Latch Outputs TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100329 www.national.com Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100329-4 DS100329-3 Functional Description The ’AC/’ACT373 contains eight D-type latches with TRI-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Truth Table Inputs LE X H H L OE H L L L Dn X L H X Outputs On Z L H O0 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH to Low transition of Latch Enable www.national.com 2 Logic Diagram DS100329-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.national.com Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V Recommended Operating Conditions Supply Voltage (VCC) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns ± 50 mA ± 50 mA −65˚C to +150˚C 175˚C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. DC Characteristics for ’AC Family Devices Symbol Parameter VCC (V) VIH Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 54AC TA = −55˚C to +125˚C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 (Note 2) VIN = VIL or VIH 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 2.4 3.7 4.7 0.1 0.1 0.1 (Note 2) VIN = VIL or VIH 3.0 4.5 5.5 IIN Maximum Input Leakage Current 5.5 0.50 0.50 0.50 V µA IOL VI = VCC, GND 12 mA 24 mA 24 mA V IOUT = 50 µA V IOH −12 mA −24 mA −24 mA V IOUT = −50 µA V VOUT = 0.1V or VCC − 0.1V V VOUT = 0.1V or VCC − 0.1V Units Conditions ± 1.0 www.national.com 4 DC Characteristics for ’AC Family Devices Symbol Parameter VCC (V) IOZ Maximum TRI-STATE Current IOLD IOHD ICC (Note 3) Minimum Dynamic Output Current Maximum Quiescent Supply Current Note 2: All outputs loaded, thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. (Continued) 54AC TA = −55˚C to +125˚C Guaranteed Limits Units Conditions 5.5 5.5 5.5 .


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