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STD5NK40Z Dataheets PDF



Part Number STD5NK40Z
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description N-CHANNEL Power MOSFET
Datasheet STD5NK40Z DatasheetSTD5NK40Z Datasheet (PDF)

STD5NK40Z-1, STD5NK40ZT4 Datasheet N-channel 400 V, 1.45 Ω typ., 3 A SuperMESH™ Power MOSFETs in IPAK and DPAK packages TAB 3 IPAK 12 G(1) D(2, TAB) S(3) TAB 23 1 DPAK Features Order codes VDS RDS(on) max. STD5NK40Z-1 STD5NK40ZT4 400 V 1.80 Ω • 100% avalanche tested • Gate charge minimized • Very low intrinsic capacitance • Zener-protected PTOT 45 W Package IPAK DPAK Applications • Switching applications Description AM01475V1 These high-voltage devices are Zener-protected N-.

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STD5NK40Z-1, STD5NK40ZT4 Datasheet N-channel 400 V, 1.45 Ω typ., 3 A SuperMESH™ Power MOSFETs in IPAK and DPAK packages TAB 3 IPAK 12 G(1) D(2, TAB) S(3) TAB 23 1 DPAK Features Order codes VDS RDS(on) max. STD5NK40Z-1 STD5NK40ZT4 400 V 1.80 Ω • 100% avalanche tested • Gate charge minimized • Very low intrinsic capacitance • Zener-protected PTOT 45 W Package IPAK DPAK Applications • Switching applications Description AM01475V1 These high-voltage devices are Zener-protected N-channel Power MOSFETs developed using the SuperMESH™ technology by STMicroelectronics, an optimization of the well-established PowerMESH™. In addition to a significant reduction in on-resistance, these devices are designed to ensure a high level of dv/dt capability for the most demanding applications. Product status link STD5NK40Z-1 STD5NK40ZT4 DS2854 - Rev 4 - September 2018 For further information contact your local STMicroelectronics sales office. www.st.com STD5NK40Z-1, STD5NK40ZT4 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter VDS Drain-source voltage VGS Gate-source voltage ID Drain current (continuous) at TC = 25 °C ID Drain current (continuous) at TC = 100 °C IDM (1) Drain current (pulsed) PTOT Total dissipation at TC = 25 °C dv/dt (2) Peak diode recovery voltage slope ESD Gate-source human body model (C = 100 pF, R = 1.5 kΩ) Tj Operating junction temperature range Tstg Storage temperature range 1. Pulse width limited by safe operating area. 2. ISD ≤ 3 A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS. Value 400 ±30 3 1.9 12 45 4.5 2.8 -55 to 150 Table 2. Thermal data SymbolParameter Rthj-case Thermal resistance junction-case Rthj-amb Thermal resistance junction-ambient Rthj-pcb (1) Thermal resistance junction-pcb 1. When mounted on an 1-inch² FR-4, 2oz Cu board. Value IPAK DPAK 2.78 100 50 Symbol IAR EAS Table 3. Avalanche characteristics Parameter Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) Value 3 130 Unit V V A A A W V/ns kV °C Unit °C/W °C/W °C/W Unit A mJ DS2854 - Rev 4 page 2/23 STD5NK40Z-1, STD5NK40ZT4 Electrical characteristics 2 Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 4. On/off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA IDSS IGSS VGS(th) RDS(on) Zero gate voltage drain current Gate-body leakage current Gate threshold voltage Static drain-source on resistance VGS = 0 V, VDS = 400 V VGS = 0 V, VDS = 400 V, TC = 125 °C (1) VDS = 0 V, VGS = ±20 V VDS = VGS, ID = 50 µA VGS = 10 V, ID = 1.5 A 1. Defined by design, not subject to production test. Min. 400 3 Typ. 3.75 1.45 Max. 1 50 ±10 4.5 1.80 Unit V µA µA µA V Ω Table 5. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance 305 Coss Output capacitance VDS = 25 V, f = 1 MHz, VGS = 0 V - 57 pF Crss Reverse transfer capacitance 11.5 Coss eq. (1) Equivalent output capacitance VGS = 0 V, VDS = 0 V to 320 V - 44 Qg Total gate charge VDD = 320 V, ID = 3 A, 11.7 17 Qgs Gate-source charge VGS = 0 to 10 V - 2.8 nC Qgd Gate-drain charge (see Figure 14. Test circuit for gate charge behavior) 5.8 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDSincreases from 0 to 80% VDSS. Symbol td(on) tr td(off) tf tr(Voff) tf tc Parameter Turn-on delay time Rise time Turn-off delay time Fall time Off-voltage rise time Fall time Cross-over time Table 6. Switching times Test conditions Min. Typ. Max. Unit VDD = 200 V, ID = 1.5 A, 9.2 RG = 4.7 Ω, VGS = 10 V 6 (see Figure 13. Test circuit for 22.5 resistive load switching times and Figure 18. Switching time waveform) - 11 - ns VDD = 320 V, ID = 3 A, 8.5 RG = 4.7 Ω, VGS = 10 V 7.5 (see Figure 15. Test circuit for inductive load switching and 14.5 diode recovery times) DS2854 - Rev 4 page 3/23 STD5NK40Z-1, STD5NK40ZT4 Electrical characteristics Table 7. Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - ISDM (1) Source-drain current (pulsed) - VSD (2) Forward on voltage ISD = 3 A, VGS = 0 V - trr Reverse recovery time ISD = 3 A, di/dt = 100 A/µs - Qrr Reverse recovery charge VDD = 40 V, Tj = 150 °C - (see Figure 15. Test circuit for IRRM Reverse recovery current inductive load switching and - diode recovery times) 3 A 12 1.6 V 145 ns 464 nC 6.4 A 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 μs, duty cycle 1.5 %. Table 8. Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ±1 mA, ID = 0 A Min. Typ. Max. Unit ±30 - - V The built-in back-to-back Zener .


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